Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
Rev. 00D
06/02/08
IS42S32200E
enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC)
is required for a single refresh operation, and no other
commands can be executed during this period. This com-
mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are “Don’t
Care”. This command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become “Don’t
Care”.The device must remain in self refresh mode for a
minimum period equal to tRAS or may remain in self refresh
mode for an indefinite period beyond that.The SELF-
REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
any other pins.The next command cannot be executed
until the device internal recovery period (tRC) has elapsed.
Once CKE goes HIGH, the NOP command must be
issued
(minimum of two clocks)
to provide time for the
completion of any internal refresh in progress. After the
self-refresh, since it is impossible to determine the ad-
dress of the last row to be refreshed, an AUTO-REFRESH
should immediately be performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGSITER command the mode
register is loaded from A0-A10. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A10 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
TRUTH TABLE – COMMANDS AND DQM OPERATION
(1)
FUNCTION
CSCS
CSCS
CS
RASRAS
RASRAS
RAS
CASCAS
CASCAS
CAS
WEWE
WEWE
WE DQM ADDR DQs
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row)
(3)
L L H H X Bank/Row X
READ (Select bank/column, start READ burst)
(4)
LHLHL/H
(8)
Bank/Col X
WRITE (Select bank/column, start WRITE burst)
(4)
L H L L L/H
(8)
Bank/Col Valid
BURST TERMINATE L H H L X X Active
PRECHARGE (Deactivate row in bank or banks)
(5)
LLHLX Code X
AUTO REFRESH or SELF REFRESH
(6,7)
LLLHXXX
(Enter self refresh mode)
LOAD MODE REGISTER
(2)
L L L L X Op-Code X
Write Enable/Output Enable
(8)
L Active
Write Inhibit/Output High-Z
(8)
H High-Z
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register.
3. A0-A10 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and DQs are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
9
Rev. 00D
06/02/08
IS42S32200E
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK
n
(1-6)
CURRENT STATE
COMMAND (ACTION) CS RAS CAS WE
Any COMMAND INHIBIT
(NOP/Continue previous operation)
HX XX
NO OPERATION
(NOP/Continue previous operation)
LH HH
Idle ACTIVE (Select and activate row) L L H H
AUTO REFRESH
(7)
LL LH
LOAD MODE REGISTER
(7)
LL LL
PRECHARGE
(11)
LL HL
Row Active READ (Select column and start READ burst)
(10)
LH LH
WRITE (Select column and start WRITE burst)
(10)
LH LL
PRECHARGE (Deactivate row in bank or banks)
(8)
LL HL
Read READ (Select column and start new READ burst)
(10)
LH LH
(Auto WRITE (Select column and start WRITE burst)
(10)
LH LL
Precharge PRECHARGE (Truncate READ burst, start PRECHARGE)
(8)
LL HL
Disabled) BURST TERMINATE
(9)
LH HL
Write READ (Select column and start READ burst)
(10)
LH LH
(Auto WRITE (Select column and start new WRITE burst)
(10)
LH LL
Precharge PRECHARGE (Truncate WRITE burst, start PRECHARGE)
(8)
LL HL
Disabled) BURST TERMINATE
(9)
LH HL
TRUTH TABLE – CKE
(1-4)
CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn
Power-Down X Maintain Power-Down L L
Self Refresh X Maintain Self Refresh L L
Clock Suspend X Maintain Clock Suspend L L
Power-Down
(5)
COMMAND INHIBIT or NOP Exit Power-Down L H
Self Refresh
(6)
COMMAND INHIBIT or NOP Exit Self Refresh L H
Clock Suspend
(7)
X Exit Clock Suspend L H
All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry H L
All Banks Idle AUTO REFRESH Self Refresh Entry H L
Reading or Writing VALID Clock Suspend Entry H L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK
n
HH
NOTES:
1. CKEn is the logic state of CKE at clock edge
n
; CKEn-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge
n
.
3. COMMANDn is the command registered at clock edge
n
, and ACTONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge
n
will put the device in the all banks idle state in time for clock edge
n+1
(provided that t
CKS
is met)
.
6. Exiting self refresh at clock edge
n
will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands
should be issued on clock edges occurring during the t
XSR period. A minimum of two NOP commands must be sent during tXSR period.
7. After exiting clock suspend at clock edge
n
, the device will resume operation and recognize the next command at clock edge
n+1
.

IS42S32200E-6BI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 64M (2Mx32) 166MHz SDRAM, 3.3v
Lifecycle:
New from this manufacturer.
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