PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 10 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
7.2 Link programmability
The number of high-speed serial channels used is programmed by CMOS input pins
LS[1:0]. For a given link consisting of a transmitter and receiver pair of PTN3700’s, the
number of channels used must be programmed identically or the link will malfunction. The
PTN3700, once programmed, will assume the corresponding serialization ratio as shown
in Table 5
. When pins LS[1:0] are both HIGH, the PTN3700 is put in a test mode which is
used for production testing purposes only and should not be used in application.
The 1-lane mode is typically meant for smaller video display formats (e.g., QVGA to
HVGA), while the 2-lane mode is typically used for display formats like HVGA and VGA.
The 3-lane mode supports larger display formats such as VGA or XGA. Please see
Section 12.1
for more information.
[1] Mode 11 is used for test purposes only.
7.3 Versatile signal mirroring programmability
In order to provide flexibility for different signal order and flow requirements in different
applications, the PTN3700 can be programmed to mirror its signal order for the parallel
and serial I/Os independently using the PSEL[1:0] inputs. The signal order also changes
as a function of the TX/RX
input by mirroring signals in such a way that the Transmitter
and Receiver in a given link can be connected without signal crossings by simply
opposing the two instances of PTN3700 and rotating one of them by 180 degrees. The
truth table for the versatile signal mirroring scheme is shown in Table 6
and Table 7. The
individual ball mappings are given in Figure 4
through Figure 11.
Table 5. Link programmability
LS1 LS0 Mode Number of
high-speed
serial channels
Supported PCLK
frequency range (MHz)
Guaranteed data
bandwidth per
channel (Mbit/s)
Guaranteed
aggregate link
bandwidth (Mbit/s)
L L 00 1 4.0 to 21.6 120 to 650 650
L H 01 2 8.0 to 43.3 120 to 650 1300
H L 10 3 20.0 to 65.0 200 to 650 1950
H H 11 reserved
[1]
reserved reserved reserved
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 11 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
[1] For PTN3700EV/G VFBGA56 package option. See also Figure 4 through Figure 11.
Table 6. Versatile signal mirroring programmability - Parallel I/O
Ball location
[1]
TX/RX
L H
PSEL0
L H L H
(Receive mode) (Transmit mode)
H3 DE DE R7 B0
G3 VS
VS R6 B1
H4 HS
HS R5 B2
G4 PCLK PCLK R4 B3
H5 B0 R7 R3 B4
G5 B1 R6 R2 B5
H6 B2 R5 R1 B6
G6 B3 R4 R0 B7
H7 B4 R3 G7 G0
G7 B5 R2 G6 G1
F7 B6 R1 G5 G2
F6 B7 R0 G4 G3
E7 G0 G7 G3 G4
E6 G1 G6 G2 G5
D7 G2 G5 G1 G6
D6 G3 G4 G0 G7
C7 G4 G3 B7 R0
C6 G5 G2 B6 R1
B7 G6 G1 B5 R2
A7 G7 G0 B4 R3
B6 R0 B7 B3 R4
A6 R1 B6 B2 R5
B5 R2 B5 B1 R6
A5 R3 B4 B0 R7
B4 R4 B3 PCLK PCLK
A4 R5 B2 HS
HS
B3 R6 B1 VS VS
A3 R7 B0 DE DE
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 12 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
[1] For PTN3700EV/G VFBGA56 package option. See also Figure 4 through Figure 11.
7.4 High-speed data channel protocol options
The PTN3700 maps the transmission protocol in accordance with the serialization mode
selected by pins LS[1:0]. In Mode 00 (1-channel), all RGB, parity and synchronization bits
are serialized onto a single 30-bit sequence. In Mode 01 (2-channel), these bits are
mapped onto two simultaneous 15-bit sequences divided across two lanes. In Mode 10
(3-channel), the 30 bits are serialized onto three simultaneous 10-bit sequences.
The serial bit mapping is different between pseudo-source-synchronous mode
(FSS = LOW) and fully source-synchronous mode (FSS = HIGH). The mapping of the
data bits in pseudo-source synchronous mode is shown in Figure 12
, Figure 13 and
Figure 14
. (Note that the CLK in Mode 01 has an asymmetrical duty cycle of 8/15). The
serial bit mapping in fully source-synchronous mode is shown in Figure 15
, Figure 16 and
Figure 17
. Note that the fully source synchronous transmission mode is not dependent on
the phase of PCLK for receiver synchronization.
Table 7. Versatile signal mirroring programmability - Serial I/O
Ball location
[1]
PSEL1
L H
A1 D2+ D0
B1 D2 D0+
C1 D1+ CLK-
D1 D1 CLK+
E1 CLK+ D1
F1 CLK D1+
G1 D0+ D2
H1 D0 D2+

PTN3700EV/G,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Serializers & Deserializers - Serdes 1.8V MOBILE INTERF
Lifecycle:
New from this manufacturer.
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