PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 15 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
7.4.3 PLL, PCLK, CLK and pixel synchronization
7.4.3.1 Pixel synchronization
PSS mode: The serial clock CLK provides the word boundaries explicitly for frame
synchronization. At the receiver side, a PLL is needed to re-generate the bit clock,
translating to a higher receiver power dissipation.
FSS mode: The serial clock CLK is truly synchronous with the serial data. Embedded
synchronization words are transmitted in the non-active display area for pixel
synchronization. The receiver PLL is powered down during this mode, hence the lower
power consumption when compared with PSS mode. The special embedded
synchronization words are guaranteed by design to never trigger false synchronization.
7.4.3.2 PLL
The PLL locks onto the PCLK input during transmit mode or the CLK input during receiver
mode. It generates an internal high-speed clock, which is phase-aligned to the input clock.
The PLL logic uses the lane select and transmit/receive status to determine the necessary
PLL bandwidth settings and PLL divider values automatically. The PLL is able to track
spread spectrum clocking to reduce EMI. The spread spectrum clock modulation
frequency can be from 30 kHz to 33 kHz.
Transmitter: The internally generated clock is always aligned to the input clock PCLK.
• PSS mode: Refer to Section 7.4.1.
• FSS mode: The output clock CLK is Double Data Rate (DDR) and both clock edges
are aligned to the data output.
Receiver:
• PSS mode: The PLL generates an internal clock at serial bit frequency and locks to
the input clock CLK.
• FSS mode: The receiver uses Double Data Rate (DDR) input clock CLK, which is
aligned to the data already.
7.4.4 HS, VS and DE signal usage in various PTN3700 modes
When frame mixing is not used in PSS mode, VS, HS, DE, R[7:0], G[7:0], B[7:0] are
treated as arbitrary user data. In this mode, PTN3700 functions as a pure serializer and
deserializer, and is unaware of the meaning or polarity of VS
, HS, DE, R[7:0], G[7:0],
B[7:0]. In FSS mode, PTN3700 makes use of VS
, HS and DE to implement pixel
synchronization with embedded sync words in the non-active display area.
When frame mixing is used, VS
, HS, DE and R[7:0], G[7:0], B[7:0] are used to implement
NXP-patented frame mixing algorithm.
Table 8
summarizes the requirements of VS, HS, DE and RGB in various modes.
