PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 31 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
Transparent top view.
Fig 23. Pinning configuration example 1
D0
VDDADEHSB0B2
D0+GNDAVSPCLKB1B3
CLK
TX/RXA1GNDVDDB6
CLK+PSEL0LS0FMG0
D1
GNDPSEL1LS1FSSG2
D1+F/XSGNDVDDG4
VDD
A0
B4
B5
B7
G1
G3
G5
D2
XSDR6R4R2R0
D2+CPOR5R3R1 R7
G6
G7
002aac935
ball A1 index
Transmitter mode
PSEL1 = 1
PSEL0 = 0
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
PCLK
HS
VS
DE
D2+ VDDA R7 R5 R3 R1
D2 GNDA R6 R4 R2 R0
D1+ TX/RX A1 GND VDD G5
D1 PSEL0 LS0 FM G3
CLK+ GND PSEL1 LS1 FSS G1
CLK F/XS GND VDD B7
VDD
A0
G7
G6
G4
G2
G0
B6
D0+ XSD PCLK B1 B3
D0 CPO B0 B2DE
B5
B4
VS
HS
ball A1 index
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B5
B4
B3
B2
B1
B0
PCLK
HS
VS
DE
Receiver mode
PSEL1 = 0
PSEL0 = 0
B6
Transparent top view.
Fig 24. Pinning configuration example 2
D2+
VDDADEHSR7R5
D2GNDAVSPCLKR6R4
D1+
TX/RXA1GNDVDDR1
D1PSEL0LS0FMG7
CLK+
GNDPSEL1LS1FSSG5
CLKF/XSGNDVDDG3
VDD
A0
R3
R2
R0
G6
G4
G2
D0+
XSDB1B3B5B7
D0CPOB2B4B6 B0
G1
G0
002aac936
ball A1 index
Transmitter mode
PSEL1 = 0
PSEL0 = 1
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
PCLK
HS
VS
DE
D0 VDDA B0 B2 B4 B6
D0+ GNDA B1 B3 B5 B7
CLK TX/RX A1 GND VDD G2
CLK+ PSEL0 LS0 FM G4
D1 GND PSEL1 LS1 FSS G6
D1+ F/XS GND VDD R0
VDD
A0
G0
G1
G3
G5
G7
R1
D2 XSD PCLK R6 R4
D2+ CPO R7 R5DE
R2
R3
VS
HS
ball A1 index
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
R0
R2
R3
R4
R5
R6
R7
PCLK
HS
VS
DE
Receiver mode
PSEL1 = 1
PSEL0 = 1
R1
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 32 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
12.3 Power decoupling configuration
The PTN3700 needs 1.8 V V
DD
and 1.8 V V
DDA
. Both can share the same voltage
regulator, and use a 10 resistor for isolation. The recommended power configuration of
the decoupling is shown in Figure 25
. It is recommended to install one 0.1 F ceramic
capacitor for each VDD pin and one 0.01 F ceramic capacitor for VDDA pin, and the lead
length between the IC power pins and decoupling capacitors should be as short as
possible.
12.4 PCB/Flex layout guideline
The high data rate at the serial I/O requires some specific implementations in the PCB and
flex layout design. The following practices can be used as guideline:
The differential pair must be routed symmetrically. Keep all four pairs of differential
signal traces the same length. The difference in trace length should be less than
20 mils.
Maintain 100 differential impedance.
Do not route signals over any plane split; use only one ground plane underneath the
differential signals.
Avoid any discontinuity for signal integrity. Differential pairs should be routed on the
same layer and the number of vias on the differential traces should be minimized. Test
points should be placed in series and symmetrically. Stubs should not be introduced
on the differential pairs.
12.5 Power-on/power-off requirement
PTN3700 does not have any external reset pin. Internally, there is Power-On Reset (POR)
circuitry to reset the whole IC at power-up. In order to guarantee that POR works properly,
the supply voltage V
DD
must be powered up from ground level, as illustrated in Figure 26.
Fig 25. Power decoupling configuration
VDD
0.1 μF 0.1 μF 0.1 μF
10 Ω
0.01 μF
VDDA
002aac937
Fig 26. Expected and unexpected power-on behavior
002aag311
Expected behavior.
Power-up from GND level enables
PTN3700 to start up correctly with
stable POR.
Unexpected behavior.
Power-up from a higher than GND level
might set PTN3700 to an unstable state
without proper POR.
V
DD
GND
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 33 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
It is recommended to have long enough of a power-off time to let V
DD
discharge
completely, reaching to ground level.
If the supply voltage V
DD
cannot be guaranteed to start from ground level, it is
recommended to hold the XSD
pin at LOW during power-on.
13. Test information
13.1 High-speed signaling channel measurements
Fig 27. XSD at LOW during power-on
002aag312
V
DD
GND
GND
XSD
Fig 28. Transmitter termination and definition for measurement of electrical parameters
Fig 29. Voltage waveforms, common mode ripple measurement (single-ended mode)
49.9 Ω ± 1 %
49.9 Ω ± 1 %
+
CLK, D0, D1 or D2
V
O(cm)
V
O(dif)
002aac101
V
I(cm)
, V
O(cm)
Dn+, CLK+
Dn, CLK
V
I(cm)ripple(p-p)
, V
O(cm)ripple(p-p)
002aac102

PTN3700EV/G,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Serializers & Deserializers - Serdes 1.8V MOBILE INTERF
Lifecycle:
New from this manufacturer.
Delivery:
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