OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

PTN3700EV/G,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 28 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
11.4 High-speed signaling channel
[1]
[2] Mode 00: UI = PCLK period / 30
Mode 01: UI = PCLK period / 15
Mode 10: UI = PCLK period / 10
[3] N is defined as the bit position, where 0 N 29 (Mode 00), 0 N 14 (Mode 01) or 0 N 9 (Mode 10).
Table 21. High-speed signaling channel SubLVDS output characteristics, Transmitter mode
V
DD
= 1.65 V to 1.95 V, T
amb
=
40
C to +85
C, unless otherwise specified. See Section 13.1 for testing information.
Symbol Parameter Conditions Min Typ Max Unit
V
O(dif)
differential output
voltage
see Figure 28 100 150 200 mV
V
O(cm)
common-mode output
voltage
see Figure 28 0.8 0.9 1.0 V
V
O(cm)ripple(p-p)
peak-to-peak ripple
common-mode output
voltage
see Figure 29 75 - +75 mV
R
o(dif)
differential output
resistance
between complimentary outputs of
any differential pair: CLK+/CLK;
D0+/D0; D1+/D1; D2+/D2
80 180 280
t
r(dif)
differential rise time from 20 % to 80 % of V
O(dif)
;
see Figure 30
200 - 500 ps
t
f(dif)
differential fall time from 80 % to 20 % of V
O(dif)
;
see Figure 30
200 - 500 ps
f
oper
operating frequency - - 325 MHz
I
O
output current output drive current per channel - - 4 mA
V
O(dif)
/V
O(dif)
relative differential
output voltage
difference
between CLK+/CLK and
Dn+/Dn, referenced to
CLK+/CLK
[1]
10 - +10 %
V
O(cm)
common-mode output
voltage difference
between CLK+/CLK and
Dn+/Dn
0.1 - +0.1 V
t
r
rise time difference t
r
(CLK+/CLK) t
r
(Dn+/Dn) 100 - +100 ps
t
f
fall time difference t
f
(CLK+/CLK) t
f
(Dn+/Dn) 100 - +100 ps
I
LO
output leakage current Shutdown or Standby mode
(high-impedance state)
3.0 - +3.0 A
t
bit(CLKH-Q)
bit time from CLK HIGH
to data output
PSS mode; Mode 00 or Mode 01;
see Table 5
, Figure 33
[2][3]
N UI
19 % UI
N UI N UI
+19% UI
ps
PSS mode: Mode 10; see
Table 5
, Figure 33
[2][3]
N UI
16 % UI
N UI N UI
+16% UI
ps
t
sk(CLK-Q)
skew time from clock
to data output
CLK edge to data output skew
time; FSS mode; see Figure 35
[2]
16 % UI 0 +16 % UI ps
%
V
OdifCLK
V
OdifDATA
–
V
OdifCLK
---------------------------------------------------------------
100 %=
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 29 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
[1]
[2] Mode 00: UI = PCLK period / 30
Mode 01: UI = PCLK period / 15
Mode 10: UI = PCLK period / 10
[3] N is defined as the bit position, where 0 N 29 (Mode 00), 0 N 14 (Mode 01) or 0 N 9 (Mode 10).
Table 22. High-speed signaling channel SubLVDS input characteristics, Receiver mode
V
DD
= 1.65 V to 1.95 V, T
amb
=
40
C to +85
C, unless otherwise specified. See Section 13.1 for testing information.
Symbol Parameter Conditions Min Typ Max Unit
V
I(dif)
differential input voltage see Figure 31 70 100 450 mV
V
th(H)i(dif)
differential input HIGH-level
threshold voltage
see Figure 32 +25 - - mV
V
th(L)i(dif)
differential input LOW-level
threshold voltage
see Figure 32 --25 mV
V
I(cm)
common-mode input voltage see Figure 31 0.4 - 1.4 V
V
I(cm)ripple(p-p)
peak-to-peak ripple
common-mode input voltage
see Figure 29 75 - +75 mV
R
i(dif)
differential input resistance internal termination resistor;
see Figure 31
80 100 120
t
r(dif)
differential rise time from 20 % to 80 % of V
I(dif)
;
see Figure 30
--800ps
t
f(dif)
differential fall time from 80 % to 20 % of V
I(dif)
;
see Figure 30
--800ps
f
oper
operating frequency - - 325 MHz
V
I(dif)
/V
I(dif)
relative differential input
voltage difference
between CLK+/CLK and
Dn+/Dn, referenced to
CLK+/CLK
[1]
10 - +10 %
V
I(cm)
common-mode input voltage
difference
between CLK+/CLK and
Dn+/Dn
0.1 - +0.1 V
t
r
rise time difference t
r
(CLK+/CLK) t
r
(Dn+/Dn) 100 - +100 ps
t
f
fall time difference t
f
(CLK+/CLK) t
f
(Dn+/Dn) 100 - +100 ps
R
pd
pull-down resistance complimentary input (Dn) to
GND; input clock inactive;
see Figure 31
-150k
I
LI
input leakage current Shutdown or Standby mode 90 - +90 A
t
bit(CLKH-D)
bit time from CLK HIGH to
data input
PSS mode; see Figure 34
[2][3]
N UI
21 % UI
N UI N UI
+21% UI
ps
t
sk(CLK-D)
skew time from clock to
data input
CLK edge to data input skew
time; FSS mode;
see Figure 35
[2]
21 % UI 0 +21 % UI ps
%
V
IdifCLK
V
IdifDATA
–
V
IdifCLK
-----------------------------------------------------------
100 %=
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 30 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
12. Application information
12.1 Typical lane and PCLK configurations
The PTN3700 supports PCLK (pixel clock) frequencies from 4 MHz to 65 MHz over 1, 2 or
3 data lanes. Table 23
shows the typical number of data lanes needed, assuming blanking
overhead of 20 %. Note that 20 % overhead is an example value for illustration/calculation
purposes only and not a requirement.
12.2 Pin configurations for various topologies of PCB
There are two input pins, PSEL1 and PSEL0, on the PTN3700 that allow for pinning order
configurations.
PSEL1 will change the pinning order of the serial signals, and allow for various topologies
of PCB or flex layout without crossing the high-speed differential traces. The example
shown in Figure 23
has set PSEL1 = 0 at receiver side, and PSEL1 = 1 at the transmitter
to avoid the traces crossing. Figure 24
shows another configuration, which has PSEL1 = 1
at receiver, and PSEL1 = 0 at transmitter.
PSEL0 can configure the pinning order of the parallel signals, and enables the easy
introduction of the PTN3700 into an existing parallel design avoiding board re-layout.
Figure 23
and Figure 24 show two configuration examples.
Table 23. Typical PCLK and number of data lanes
Panel Horizontal Vertical Color
bit
Other
bits
Frame
rate
(Hz)
Blanking
overhead
Pixel
clock
(MHz)
Serial aggregate data rate
(Mbit/s)
1-lane 2-lane 3-lane
QVGA 240 320 18 12 60 20 % 5.5 165.9
WQVGA 400 240 18 12 60 20 % 6.9 207.4
CIF+ 352 416 18 12 60 20 % 10.5 316.3 316.3
HVGA 320 480 24 6 60 20 % 11.1 331.8 331.8
VGA 640 480 24 6 60 20 % 22.1 663.6 663.6
WVGA 854 480 24 6 60 20 % 29.5 885.4 885.4
SVGA 800 600 24 6 60 20 % 34.6 1036.8 1036.8
XGA 1024 768 24 6 60 20 % 56.6 1698.7
720p 1280 720 24 6 60 15 % 63.6 1909.7
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

PTN3700EV/G,118

Mfr. #:
Buy PTN3700EV/G,118
Manufacturer:
NXP Semiconductors
Description:
Serializers & Deserializers - Serdes 1.8V MOBILE INTERF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet