PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 5 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
6. Pinning information
6.1 Pinning
Fig 3. Ball configuration for VFBGA56
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PTN3700EV/G
Transparent top view
ball A1
index area
A
1234567
B
C
D
E
F
G
H
56-ball, 7 8 grid; transparent top view 56-ball, 7 8 grid; transparent top view
Fig 4. VFBGA56 ball mapping - Transmitter mode
(TX/RX
= HIGH); PSEL[1:0] = 00b
Fig 5. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 01b
56-ball, 7 8 grid; transparent top view 56-ball, 7 8 grid; transparent top view
Fig 6. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 10b
Fig 7. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 11b
D2+ VDDA DE HS B0 B2
123456
D2− GNDA VS PCLK B1 B3
A
B
D1+ TX/RX A1 GND VDD B6C
D1− PSEL0 LS0 FM G0D
CLK+ GND PSEL1 LS1 FSS G2E
CLK− F/XS GND VDD G4F
VDD
A0
B4
7
B5
B7
G1
G3
G5
D0+ XSD R6 R4 R2 R0G
D0− CPO R5 R3 R1HR7
G6
G7
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D2+ VDDA DE HS R7 R5
123456
D2− GNDA VS PCLK R6 R4
A
B
D1+ TX/RX A1 GND VDD R1C
D1− PSEL0 LS0 FM G7D
CLK+ GND PSEL1 LS1 FSS G5E
CLK− F/XS GND VDD G3F
VDD
A0
R3
7
R2
R0
G6
G4
G2
D0+ XSD B1 B3 B5 B7G
D0− CPO B2 B4 B6HB0
G1
G0
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D0− VDDA DE HS B0 B2
123456
D0+ GNDA VS PCLK B1 B3
A
B
CLK− TX/RX A1 GND VDD B6C
CLK+ PSEL0 LS0 FM G0D
D1− GND PSEL1 LS1 FSS G2E
D1+ F/XS GND VDD G4F
VDD
A0
B4
7
B5
B7
G1
G3
G5
D2− XSD R6 R4 R2 R0G
D2+ CPO R5 R3 R1HR7
G6
G7
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D0− VDDA DE HS R7 R5
123456
D0+ GNDA VS PCLK R6 R4
A
B
CLK− TX/RX A1 GND VDD R1C
CLK+ PSEL0 LS0 FM G7D
D1− GND PSEL1 LS1 FSS G5E
D1+ F/XS GND VDD G3F
VDD
A0
R3
7
R2
R0
G6
G4
G2
D2− XSD B1 B3 B5 B7G
D2+ CPO B2 B4 B6HB0
G1
G0
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