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PTN3700EV/G,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 22 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
[1] Worst-case data pattern for power dissipation is used: alternating vertical stripes. The colors of the stripes correspond to the data
pattern: RGB[23:0] = 0xAA AAAA (odd stripes) / RGB[23:0] = 0x55 5555 (even stripes).
[2] Based on receiver output load (per output) of 16 pF. The loaded outputs are: PCLK, R[7:0], G[7:0], B[7:0], HS
, VS and DE.
Receiver mode, PSS mode (TX/RX = LOW; FSS = LOW)
[2]
I
DD
supply current Shutdown mode;
T
amb
= 40 Cto+60C
-410A
Standby mode;
T
amb
= 40 Cto+60C
-410A
Active mode
[1]
PCLK = 6 MHz; Mode 00 - 8 10.7 mA
PCLK = 12 MHz; Mode 00 - 14 16.5 mA
PCLK = 20 MHz; Mode 00 - 22 25 mA
PCLK = 8 MHz; Mode 01 - 8.5 11 mA
PCLK = 22 MHz; Mode 01 - 16 19.5 mA
PCLK = 40 MHz; Mode 01 - 25 31 mA
PCLK = 20 MHz; Mode 10 - 14 17.8 mA
PCLK = 40 MHz; Mode 10 - 22.5 28 mA
PCLK = 65 MHz; Mode 10 - 34 40 mA
Receiver mode, FSS mode (TX/RX
= LOW; FSS = HIGH)
[2]
I
DD
supply current Shutdown mode;
T
amb
= 40 Cto+60C
-410A
Standby mode;
T
amb
= 40 Cto+60C
-410A
Active mode
[1]
PCLK = 6 MHz; Mode 00 - 7.5 10.2 mA
PCLK = 12 MHz; Mode 00 - 13 15.5 mA
PCLK = 20 MHz; Mode 00 - 20.6 23.6 mA
PCLK = 8 MHz; Mode 01 - 8.1 10.6 mA
PCLK = 22 MHz; Mode 01 - 15.4 18.6 mA
PCLK = 40 MHz; Mode 01 - 23.4 29.3 mA
PCLK = 20 MHz; Mode 10 - 13.5 17.3 mA
PCLK = 40 MHz; Mode 10 - 21.8 26.9 mA
PCLK = 65 MHz; Mode 10 - 33 38 mA
Table 16. Static characteristics
…continued
T
amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 23 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
11. Dynamic characteristics
11.1 Transmitter mode
Table 17. Dynamic characteristics for Transmitter mode
V
DD
= 1.65 V to 1.95 V, T
amb
=
40
C to +85
C, unless otherwise specified.
All CMOS input signals’ rise time and fall time to Transmitter are stipulated to be from 1 ns to 15 ns.
Symbol Parameter Conditions Min Typ Max Unit
f
i(PCLK)
input frequency on pin
PCLK
Mode 00; see Table 5 4.0 - 21.6 MHz
Mode 01; see Table 5
8.0 - 43.3 MHz
Mode 10; see Table 5
20.0 - 65.0 MHz
i(PCLK)
input duty cycle on pin
PCLK
33 - 67 % T
PCLK
t
su(D-PCLK)
set-up time from
data input to PCLK
2.0--ns
t
h(D-PCLK)
hold time from data input
to PCLK
2.0--ns
t
jit(cc)
cycle-to-cycle jitter time PCLK 300 - +300 ps
B
PLL(loop)
PLL loop bandwidth 3 dB corner frequency of
PLL loop filter response
0.02 f
i(PCLK)
0.03 f
i(PCLK)
0.05 f
i(PCLK)
MHz
Fig 19. AC timing diagram - Transmitter mode
002aab367
0.7V
DD
0.3V
DD
0.7V
DD
0.3V
DD
PCLK
VS, HS, DE,
R[7:0], G[7:0], B[7:0]
t
su(D-PCLK)
t
h(D-PCLK)
PTN3700 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 October 2011 24 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
11.2 Receiver mode
Table 18. Dynamic characteristics for Receiver mode
V
DD
= 1.65 V to 1.95 V, T
amb
=
40
C to +85
C, unless otherwise specified.
CMOS output load C
L
=16pF.
Symbol Parameter Conditions Min Typ Max Unit
f
o(PCLK)
output frequency on
pin PCLK
Mode 00; see Table 5 4.0 - 21.6 MHz
Mode 01; see Table 5
8.0 - 43.3 MHz
Mode 10; see Table 5
20.0 - 65.0 MHz
o(PCLK)
output duty cycle on
pin PCLK
Mode 00 or Mode 10;
F/XS
=1
45 50 55 % T
PCLK
Mode 01; F/XS = 1 48 53 59 % T
PCLK
t
sk(Q)
data output skew time Mode 00; F/XS =1 0.5 0 1.5 ns
Mode 01; F/XS
=1 0.5 0 0.8 ns
Mode 10; F/XS
=1 0.5 0 0.8 ns
Mode 00; F/XS
=0 3.0 0 2.0 ns
Mode 01; F/XS
=0 0.5 0 2.5 ns
Mode 10; F/XS
=0 1.4 0 3.0 ns
t
jit(r)PCLK
PCLK rise jitter time 0.6 0 0.6 ns
t
r
rise time CMOS signals
Mode 00; F/XS
= 0 8 - 18 ns
Mode 00; F/XS
= 1 4 - 10 ns
Mode 01; F/XS
= 0 4 - 10 ns
Mode 01; F/XS
=11- 3ns
Mode 10; F/XS
= 0 4 - 10 ns
Mode 10; F/XS
=11- 3ns
t
f
fall time CMOS signals
Mode 00; F/XS
= 0 8 - 18 ns
Mode 00; F/XS
= 1 4 - 10 ns
Mode 01; F/XS
= 0 4 - 10 ns
Mode 01; F/XS
=11- 3ns
Mode 10; F/XS
= 0 4 - 10 ns
Mode 10; F/XS
=11- 3ns
B
PLL(loop)
PLL loop bandwidth 3 dB corner frequency of
PLL loop filter response
0.09 f
o(PCLK)
0.11 f
o(PCLK)
0.14 f
o(PCLK)
MHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

PTN3700EV/G,118

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Manufacturer:
NXP Semiconductors
Description:
Serializers & Deserializers - Serdes 1.8V MOBILE INTERF
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