PTN3700EV/G,118 Datasheet PTN3700EV/G,118 | P16-P18

Product data sheet Rev. 3 — 12 October 2011 16 of 43

NXP Semiconductors

PTN3700

1.8 V simple mobile interface link bridge IC

[1] ‘X’ signifies that PTN3700 handles this signal transparently, i.e., data is transmitted and received as-is.

[2] ‘R, G, B’ signifies that R, G, B video data have to be input according to the exact chosen pin configuration of

PTN3700, specifically:

a) Bit order reversal is not allowed, even if both the transmit data and receive data are reversed in bit order.

For example, the MSB of ‘R’ color from video source must be input as ‘R7’.

b) ‘R’ must be used for red color, ‘G’ for green color, and ‘B’ for blue color.

7.4.4.1 PSS mode

, VS and DE are treated by PTN3700 in the same way as RGB signals in PSS mode;

that is, HS

, VS, and DE are serialized and transmitted transparently by the PTN3700

transmitter, and transparently received and deserialized by PTN3700 receiver. Data

Enable (DE) signal is typically used to signify the active display area from the non-active

display area.

In the case that advanced frame mixing is not used:

• DE signal can be tied HIGH or LOW, for displays not using DE signal.

• HS and VS can be active HIGH or active LOW.

7.4.4.2 FSS mode

In FSS mode, PTN3700 uses true source synchronous transmission with a serial

Double Data Rate (DDR) bit clock for the serial data.

FSS mode requires the following operating conditions:

• Active LOW HS

• Active LOW VS

• Active HIGH DE

In FSS mode, DE = 1 means active video, and PTN3700 generates embedded sync

words when DE = 0. DE, VS

and HS must be actively driven according to the typical video

screen figure shown in Figure 18

Table 8. VS, HS, DE, and RGB requirements

[1][2]

FSS Mode FM VS, HS DE R, G, B A[1:0]

LOW PSS HIGH active LOW active HIGH R, G, B X

LOW X X X X

HIGH FSS HIGH active LOW active HIGH R, G, B X

LOW active LOW active HIGH X X

Product data sheet Rev. 3 — 12 October 2011 17 of 43

NXP Semiconductors

PTN3700

1.8 V simple mobile interface link bridge IC

7.5 Power modes

The PTN3700 has three different power modes to minimize power consumption of the link

as a function of link activity: Shutdown mode, Standby mode, and Active mode. The truth

table for the three power modes is shown in Table 9

and Table 10.

• Shutdown mode: By driving input pin XSD LOW, the PTN3700 assumes lowest

power mode. All internal logic circuits are reset during this mode, and the link is

completely inactive. The transmitter high-speed serial output channels are put in

high-impedance state, and the receiver high-speed serial input channels are pulled

LOW. The receiver CMOS parallel outputs will all be set HIGH with the exception of

DE and PCLK which are reset LOW. However, the input buffers for the transmitter

remain active, so it is recommended to stop PCLK and RGB data to achieve the

lowest Shutdown mode power.

• Standby mode: When pin XSD is set HIGH but no input clock is active, the PTN3700

detects inactivity of the clock

and remains in a low-power Standby mode until an

active input clock is detected. The transmitter serial outputs, receiver serial inputs and

receiver parallel outputs all behave identically to their respective states in Shutdown

mode.

• Active mode: When pin XSD is set HIGH and an active input clock is detected,

PTN3700 will assume normal link operation. Current consumption depends on the

PCLK frequency, number of lanes, FSS/PSS mode, data pattern, etc.

3 numbers correspond to [DE, HS, VS]

Fig 18. Typical video screen

002aac803

000

001

010

011 011

010

011

010

HS = 0

HS = 1

001 011

001 011 011 011

011

active video

111

VS = 0

VS = 1

3. The PTN3700 clock detection circuit identifies the clock as inactive when the PCLK input signal frequency is less than 500 kHz.

Table 9. Power modes - Transmitter mode

Inputs Power mode Outputs

XSD PCLK D0+, D0, D1+, D1, D2+, D2 CLK+, CLK

L X Shutdown high-Z high-Z

H stopped Standby high-Z high-Z

H running Active active serial data active

Product data sheet Rev. 3 — 12 October 2011 18 of 43

NXP Semiconductors

PTN3700

1.8 V simple mobile interface link bridge IC

7.6 Link error detection and correction

In Transmitter mode, PTN3700 calculates an odd parity bit and merges this into the

serialized output data stream to allow the receiver to detect whether parity has been

violated for its received input data. The parity bit CP is calculated across the 27-bit input

data word (R[7:0], G[7:0], B[7:0], HS

, VS and DE) for every pixel transmitted, as shown in

Table 11

. Note that the auxiliary bits A[1:0] are excluded from the parity calculation.

In Receiver mode, the received encoded parity bit CP is compared against the received

27-bit input data word (R[7:0], G[7:0], B[7:0], HS

, VS and DE) for every pixel, and an error

is flagged by setting parity error output CPO HIGH for the duration of the pixel clock period

in which the error was detected. Note that the auxiliary output bits A[1:0] are excluded

from the parity detection.

In addition, during the pixel clock period in which the error occurs, the last valid pixel word

is output to R[7:0], G[7:0], B[7:0], HS

, VS and DE instead of the current erroneous pixel

data. The last valid pixel word is defined as the data prior to the first parity error detected

in any concatenation of parity errors.

If a parity error is detected but no valid previous pixel information is available, the receiver

will output values R[7:0] = G[7:0] = B[7:0] = HS

= VS = HIGH, and DE = LOW. The truth

table for receiver parity function is shown in Table 12

. Note that the auxiliary bits A[1:0] are

not affected by the last valid pixel repetition.

Table 10. Power modes - Receiver mode

Inputs State of serial data inputs

D0+, D0, D1+, D1, D2+, D2

Power

mode

Data Outputs

XSD CLK+, CLK R[7:0], G[7:0],

B[7:0], HS, VS

DE, PCLK

L X or floating resistively pulled H or L Shutdown H L

H stopped resistively pulled H or L Standby H L

H running normal receiver state Active active data active

Table 11. Parity encoding function table - Transmitter mode

Inputs Encoded parity bit

XSD PCLK  of inputs = H

(R[7:0], G[7:0], B[7:0], HS,VS,DE)

H running odd L

H running even H

H stopped X or floating undefined

L X or floating X or floating undefined

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P43

PTN3700EV/G,118

Mfr. #:

Buy PTN3700EV/G,118

Manufacturer:

NXP Semiconductors

Description:

Serializers & Deserializers - Serdes 1.8V MOBILE INTERF

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

PTN3700EV/G,118