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SC16IS741AIPWJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 25 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS
/RTS change of
state from LOW to HIGH. The IRQ
output signal is activated in response to interrupt
generation. Table 20
shows the Interrupt Enable Register bit settings.
[1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
Table 20. Interrupt Enable Register bits description
Bit Symbol Description
7IER[7]
[1]
CTS interrupt enable
logic 0 = disable the CTS
interrupt (normal default condition)
logic 1 = enable the CTS
interrupt
6IER[6]
[1]
RTS interrupt enable
logic 0 = disable the RTS
interrupt (normal default condition)
logic 1 = enable the RTS interrupt
5IER[5]
[1]
Xoff interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4IER[4]
[1]
Sleep mode
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 7.6 “
Sleep mode” for details.
3 IER[3] reserved
2 IER[2] Receive Line Status interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit Holding Register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0 IER[0] Receive Holding Register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 26 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 21
shows Interrupt Identification Register bit settings.
Table 21. Interrupt Identification Register bits description
Bit Symbol Description
7:6 IIR[7:6] mirror the contents of FCR[0]
5:1 IIR[5:1] 5-bit encoded interrupt. See Table 22
.
0 IIR[0] interrupt status
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Table 22. Interrupt source
Priority
level
IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt
1 0 0 0 1 1 0 Receiver Line Status error
2 0 0 1 1 0 0 Receiver time-out interrupt
2 0 0 0 1 0 0 RHR interrupt
3 000010THR interrupt
4 000000modem interrupt
6 0 1 0 0 0 0 received Xoff signal/
special character
7 100000CTS
, RTS change of state from
active (LOW) to inactive
(HIGH)
SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 27 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.10 Enhanced Features Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 23
shows the enhanced feature register bit settings.
8.11 Division registers (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Table 23. Enhanced Features Register bits description
Bit Symbol Description
7EFR[7]CTS
flow control enable
logic 0 = CTS
flow control is disabled (normal default condition)
logic 1 = CTS
flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS
pin.
6EFR[6]RTS
flow control enable.
logic 0 = RTS
flow control is disabled (normal default condition)
logic 1 = RTS
flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the
receiver FIFO resume transmission trigger level TCR[7:4] is reached.
5 EFR[5] Special character detect
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logical 1 to indicate a special character has been detected.
4 EFR[4] Enhanced functions enable bit
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] so
that they can be modified.
3:0 EFR[3:0] Combinations of software flow control can be selected by programming these
bits. See Table 4 “
Software flow control options (EFR[3:0])”.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16IS741AIPWJ

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Manufacturer:
NXP Semiconductors
Description:
UART Interface IC SC16IS741AIPW/TSSOP16///REEL 13 Q1 NDP
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