SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 45 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 36. SPI-bus timing specifications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
=2.5V
0.2 V, T
amb
=
40
Cto+85
C; or V
DD
=3.3V
0.3 V, T
amb
=
40
Cto+95
C; and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
TR
CS HIGH to SO 3-state delay time C
L
= 100 pF - - 100 ns
t
CSS
CS to SCLK setup time 100 - - ns
t
CSH
CS to SCLK hold time 20 - - ns
t
DO
SCLK fall to SO valid delay time C
L
= 100 pF - - 100 ns
t
DS
SI to SCLK setup time 100 - - ns
t
DH
SI to SCLK hold time 20 - - ns
t
CP
SCLK period t
CL
+ t
CH
250 - - ns
t
CH
SCLK HIGH time 100 - - ns
t
CL
SCLK LOW time 100 - - ns
t
CSW
CS HIGH pulse width 200 - - ns
t
d(int_clr)tx
transmit interrupt clear delay time 200 - - ns
t
d(int_clr)rx
receive interrupt clear delay time 200 - - ns
t
w(rst)
reset pulse width 3 - - s
Fig 30. Detailed SPI-bus timing
t
CSH
t
CSS
t
CL
t
CH
t
CSH
t
DO
t
TR
t
DS
t
DH
SO
SI
SCLK
CS
002aab066
t
CSW
