SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 36 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
rising edge of SCL will reset the I
2
C address decoder. As a result, the SC16IS741A locks
into the I
2
C matching slave address (configured by A1 and A0) for only one I
2
C access
cycle.
In the SC16IS741A, the I
2
C address decoder gets reset on every STOP condition and
restarts after every START condition. Any glitches occurring on the SDA line during SCL
LOW time between the START clock and the R/W clock are not allowed. These glitches
might cause the SC16IS741A not to acknowledge its own I
2
C-bus address or to ACK the
wrong I
2
C-bus address.
10.4 Use of subaddresses
When a master communicates with the SC16IS741A it must send a subaddress in the
byte following the slave address byte. This subaddress is the internal address of the word
the master wants to access for a single-byte transfer, or the beginning of a sequence of
locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device
address, it does not contain a direction (R/W
) bit, and like any byte transferred on the bus
it must be followed by an acknowledge.
Table 30
shows the breakdown of the subaddress (register address) byte. Bit 0 is not
used, bits [2:1] are both set to zeroes, bits [6:3] are used to select one of the device’s
internal registers, and bit 7 is not used.
A register write cycle is shown in Figure 18
. The START is followed by a slave address
byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a
STOP signal. The subaddress indicates which register the master wants to access, and
the data bytes which follow will be written one after the other to the subaddress location.
Table 30
and Table 31 show the bits’ presentation at the subaddress byte for I
2
C-bus and
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I
2
C-bus interface, but it is used by the
SPI interface to indicate a read or a write operation.
The register read cycle (see Figure 19) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated
START followed again by the device address, but this time with the direction bit set to
‘read’. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signaling the end of transfer. The cycle is terminated
by a STOP signal.
White block: host to SC16IS741A
Gray block: SC16IS741A to host
(1) See Table 30
for additional information.
Fig 18. Master writes to slave
S SLAVE ADDRESS
002aab047
W A REGISTER ADDRESS
(1)
A nDATA A P
