SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 41 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
[1] A detailed description of the I
2
C-bus specification, with applications, is given in user manual UM10204: “I
2
C-bus specification and user
manual”. This may be found at www.nxp.com/documents/user_manual/UM10204.pdf
.
[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3] 2 XTAL1 clocks or 3 s, whichever is less.
[4] The device will not acknowledge if an I
2
C-bus transaction occurs during the ‘SCL delay time after reset’.
Table 34. I
2
C-bus timing specifications
[1]
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
=2.5V
0.2 V, T
amb
=
40
Cto+85
C; or V
DD
=3.3V
0.3 V, T
amb
=
40
Cto+95
C; and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF, except SDA output load = 400 pF.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode
I
2
C-bus
Unit
Min Max Min Max
f
SCL
SCL clock frequency
[2]
0 100 0 400 kHz
t
BUF
bus free time between a STOP and START
condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START condition 4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.7 - 0.6 - s
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;ACK
data valid acknowledge time - 0.6 - 0.6 s
t
VD;DAT
data valid time SCL LOW to
data out valid
-0.6-0.6ns
t
SU;DAT
data set-up time 250 - 150 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
f
fall time of both SDA and SCL signals - 300 - 300 ns
t
r
rise time of both SDA and SCL signals - 1000 - 300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
t
d(int_v)modem
modem interrupt valid delay time 0.2 - 0.2 - s
t
d(int_clr)modem
modem interrupt clear delay time 0.2 - 0.2 - s
t
d(int_v)rx
receive interrupt valid delay time 0.2 - 0.2 - s
t
d(int_clr)rx
receive interrupt clear delay time 0.2 - 0.2 - s
t
d(int_clr)tx
transmit interrupt clear delay time 1.0 - 0.5 - s
t
d(rst-SCL)
SCL delay time after reset
[3][4]
3-3-s
t
d(SCL-A)
delay time from SCL to address - 30 - 30 ns
t
d(SDA-A)
delay time from SDA to address - 30 - 30 ns
t
d(A-SCL)
delay time from address to SCL - 30 - 30 ns
t
d(A-SDA)
delay time from address to SDA - 30 - 30 ns
t
w(rst)
reset pulse width 3 - 3 - s
