SC16IS741AIPWJ Datasheet SC16IS741AIPWJ | P7-P9

Product data sheet Rev. 1 — 18 March 2013 7 of 55

NXP Semiconductors

SC16IS741A

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.1 Auto RTS

Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS

are stored in the TCR or FCR. RTS

is active if the RX FIFO level is below the halt trigger

level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS

de-asserted. The sending device (for example, another UART) may send an additional

character after the trigger level is reached (assuming the sending UART has another

character to send) because it may not recognize the de-assertion of RTS

until it has

begun sending the additional character. RTS is automatically re-asserted once the

receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This

re-assertion allows the sending device to resume transmission.

7.2.2 Auto CTS

Figure 6 shows CTS functional timing. The transmitter circuitry checks CTS before

sending the next data byte. When CTS

is active, the transmitter sends the next byte. To

stop the transmitter from sending the following byte, CTS

must be de-asserted before the

middle of the last stop bit that is currently being sent. The auto CTS

function reduces

interrupts to the host system. When flow control is enabled, CTS

level changes do not

trigger host interrupts because the device automatically controls its own transmitter.

Without auto CTS

, the transmitter sends any data present in the transmit FIFO and a

receiver overrun error may result.

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1

Fig 5. RTS functional timing

start

character

start

character

N + 1

startstop stopRX

RTS

receive

FIFO

read

N N + 112

002aab040

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS

goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the current

character, but it does not send the next character.

(3) When CTS

goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6. CTS functional timing

start bit 0 to bit 7 stopTX

CTS

002aab041

start stop

bit 0 to bit 7

Product data sheet Rev. 1 — 18 March 2013 8 of 55

NXP Semiconductors

SC16IS741A

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.3 Software flow control

Software flow control is enabled through the enhanced feature register and the Modem

Control Register. Different combinations of software flow control can be enabled by setting

different combinations of EFR[3:0]. Table 4

shows software flow control options.

There are two other enhanced features relating to software flow control:

• Xon Any function (MCR[5]): Receiving any character will resume operation after

recognizing the Xoff character. It is possible that an Xon1 character is recognized as

an Xon Any character, which could cause an Xon2 character to be written to the RX

FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the

RX FIFO.

7.3.1 RX

When software flow control operation is enabled, the SC16IS741A will compare incoming

data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be

received sequentially). When the correct Xoff characters are received, transmission is

halted after completing transmission of the current character. Xoff detection also sets

IIR[4] (if enabled via IER[5]) and causes IRQ

to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

Table 4. Software flow control options (EFR[3:0])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow control

0 0 X X no transmit flow control

1 0 X X transmit Xon1, Xoff1

0 1 X X transmit Xon2, Xoff2

1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 no receive flow control

X X 1 0 receiver compares Xon1, Xoff1

X X 0 1 receiver compares Xon2, Xoff2

1011transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1111transmit Xon1 and Xon2, Xoff1 and Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0011no transmit flow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 1 — 18 March 2013 9 of 55

NXP Semiconductors

SC16IS741A

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.3.2 TX

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level

programmed in TCR[3:0] or the selectable trigger level in FCR[7:6]

Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level

programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in

FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,

or 7 bits, then the 5, 6, or 7 least significant bits of XOFF1/XOFF2 or XON1/XON2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but

this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled

simultaneously. Figure 7

shows an example of software flow control.

Fig 7. Example of software flow control

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

RECEIVE FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

UART2UART1

002aaa229

data

Xoff–Xon–Xoff

compare

programmed

Xon-Xoff

characters

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SC16IS741AIPWJ

Mfr. #:

Buy SC16IS741AIPWJ

Manufacturer:

NXP Semiconductors

Description:

UART Interface IC SC16IS741AIPW/TSSOP16///REEL 13 Q1 NDP

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