SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 37 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
White block: host to SC16IS741A
Gray block: SC16IS741A to host
(1) See Table 30
for additional information.
Fig 19. Master read from slave
S SLAVE ADDRESS
002aab048
W A REGISTER ADDRESS
(1)
A
NA P
S SLAVE ADDRESS R A
nDATA A LAST DATA
Table 30. Register address byte (I
2
C)
Bit Name Function
7 - not used
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
0 - not used
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SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 38 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
11. SPI operation
R/W = 0; A[3:0] = register address; CH1 = 0, CH0 = 0
a. Register write
R/W = 1; A[3:0] = register address; CH1 = 0, CH0 = 0
b. Register read
R/W = 0; A[3:0] = 0000; CH1 = 0, CH0 = 0
c. FIFO write cycle
R/W = 1; A[3:0] = 0000; CH1 = 0, CH0 = 0
d. FIFO read cycle
(1) Last bit (D0) of the last byte to be written to the transmit FIFO.
(2) Last bit (D0) of the last byte to be read from the receive FIFO.
Fig 20. SPI operation
SI
A1A2A3
R/W
SCLK
CH1A0
XCH0 D6D7 D4D5 D2D3 D0D1
002aab433
SI
A1A2A3
R/W
SCLK
CH1A0
XCH0
002aab434
SO
D6D7 D4D5 D2D3 D0D1
SI
A1A2A3
R/W
SCLK
CH1A0 XCH0 D6D7 D4D5 D2D3 D0D1
002aab435
D6D7 D4D5 D2D3 D0D1
last bit
(1)
SI
A1A2A3
R/W
SCLK
CH1A0 XCH0
002aab436
SO
D6D7 D4D5 D2D3 D0D1
D0D1
last bit
(2)
D6D7 D4D5 D2D3
SC16IS741A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 18 March 2013 39 of 55
NXP Semiconductors
SC16IS741A
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
12. Limiting values
[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present.
4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.
13. Static characteristics
Table 31. Register address byte (SPI)
Bit Name Function
7R/W
1: read from UART
0: write to UART
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
0 - not used
Table 32. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.3 +4.6 V
V
I
input voltage any input 0.3 +5.5
[1]
V
I
I
input current any input 10 +10 mA
I
O
output current any output 10 +10 mA
P
tot
total power dissipation - 300 mW
P/out power dissipation per output - 50 mW
T
amb
ambient temperature operating
V
DD
=2.5V 0.2 V 40 +85 C
V
DD
=3.3V 0.3 V 40 +95 C
T
j
junction temperature - +125 C
T
stg
storage temperature 65 +150 C
Table 33. Static characteristics
V
DD
=2.5V
0.2 V, T
amb
=
40
Cto+85
C; or V
DD
=3.3V
0.3 V, T
amb
=
40
Cto+95
C; unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V Unit
Min Max Min Max
Supplies
V
DD
supply voltage 2.3 2.7 3.0 3.6 V
I
DD
supply current operating; no load - 6.0 - 6.0 mA
Inputs I2C/SPI
, RX, CTS
V
IH
HIGH-level input voltage 1.6 5.5
[1]
2.0 5.5
[1]
V
V
IL
LOW-level input voltage - 0.6 - 0.8 V
I
L
leakage current input; V
I
= 0 V or 5.5 V
[1]
-1-1A
C
i
input capacitance - 3 - 3 pF

SC16IS741AIPWJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC SC16IS741AIPW/TSSOP16///REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
Delivery:
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