SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 12 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
6.3 Internal registers
The SC16C852 provides two sets of internal registers (A and B) consisting of 25 registers
each for monitoring and controlling the functions of each channel of the UART. These
registers are shown in Table 5.
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
[3] Second special registers are accessible only when EFCR[0] = 1.
[4] Enhanced feature registers are only accessible when LCR = 0xBF.
[5] First extra feature registers are only accessible when EFCR[2:1] = 01b.
[6] Second extra feature registers are only accessible when EFCR[2:1] = 10b.
Table 5. Internal registers decoding
A2 A1 A0 Read mode Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)
[1]
0 0 0 Receive Holding Register Transmit Holding Register
0 0 1 Interrupt Enable Register Interrupt Enable Register
0 1 0 Interrupt Status Register FIFO Control Register
0 1 1 Line Control Register Line Control Register
1 0 0 Modem Control Register Modem Control Register
1 0 1 Line Status Register Extra Feature Control Register (EFCR)
1 1 0 Modem Status Register n/a
1 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0 0 0 LSB of Divisor Latch LSB of Divisor Latch
0 0 1 MSB of Divisor Latch MSB of Divisor Latch
Second special register set (TXLVLCNT/RXLVLCNT)
[3]
0 1 1 Transmit FIFO Level Count n/a
1 0 0 Receive FIFO Level Count n/a
Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)
[4]
0 1 0 Enhanced Feature Register Enhanced Feature Register
1 0 0 Xon1 word Xon1 word
1 0 1 Xon2 word Xon2 word
1 1 0 Xoff1 word Xoff1 word
1 1 1 Xoff2 word Xoff2 word
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)
[5]
0 1 0 Transmit FIFO Interrupt Level Transmit FIFO Interrupt Level
1 0 0 Receive FIFO Interrupt Level Receive FIFO Interrupt Level
1 1 0 Flow Control Count High Flow Control Count High
1 1 1 Flow Control Count Low Flow Control Count Low
Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)
[6]
0 1 0 Clock Prescaler Clock Prescaler
1 0 0 RS-485 turn-around Timer RS-485 turn-around Timer
1 1 0 Additional Feature Control Register 2 Additional Feature Control Register 2
1 1 1 Additional Feature Control Register 1 Additional Feature Control Register 1
