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SC16C852IBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 25 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit
FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16× clock rate. After 7
1
⁄
2
clocks, the start bit time should be
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 11. Interrupt Enable Register bits description
Bit Symbol Description
7 IER[7] CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C852 issues an interrupt when
the
CTSA/CTSB pin transitions from a logic 0 to a logic 1.
6 IER[6] RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C852 issues an interrupt when
the
RTSA/RTSB pin transitions from a logic 0 to a logic 1.
5 IER[5] Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the receive Xoff interrupt
4 IER[4] Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 26 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts
(IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the
following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR, or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, setting IER[3:0] puts the SC16C852 in the FIFO polled mode of
operation. In this mode, interrupts are not generated and the user must poll the LSR
register for TX and/or RX data status. Since the receiver and transmitter have separate
bits in the LSR either or both can be used in the polled mode by selecting respective
transmit or receive control bit(s).
• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
• LSR[5] will indicate when the transmit FIFO is empty.
• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
• LSR[7] will show if any FIFO data errors occurred.
1 IER[1] Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be
issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO
modes, this interrupt will be issued whenever the FIFO is empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
0 IER[0] Receive Holding Register interrupt. In the non-FIFO mode, this interrupt will be
issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the programmed
trigger level or is cleared when the FIFO drops below the trigger level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
Table 11. Interrupt Enable Register bits description
…continued
Bit Symbol Description
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 27 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)
In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if
FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)
In this mode, the Transmit Ready (TXRDY) is set when the transmit FIFO is below the
programmed trigger level. The Receive Ready (RXRDY) is set when the receive FIFO fills
to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
7.3.2 FIFO mode
Table 12. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode
[1]
.
These bits are used to set the trigger levels for receive FIFO interrupt and
flow control. The SC16C852 will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to
Table 13.
5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode
[2]
.
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 14.
3 FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C852 is in the non-FIFO
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO, the
TXRDYA/TXRDYB pin will be a logic 0.
Once active, the
TXRDYA/TXRDYB pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C852 is in non-FIFO mode,
or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least
one character in the receive FIFO, the
RXRDYA/RXRDYB pin will be a
logic 0. Once active, the
RXRDYA/RXRDYB pin will go to a logic 1 when
there are no more characters in the receiver.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

SC16C852IBS,157

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Buy SC16C852IBS,157
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32HVQFN
Lifecycle:
New from this manufacturer.
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