SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 8 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
INTB/n.c. 29 21 O When 16/68 pin is at logic 1 or unconnected, this output becomes channel B
interrupt output. The output state is defined by the user through the software
setting of MCR[3]. INTB is set to the active mode and
OP2B output to a logic 0
when MCR[3] is set to a logic 1. INTB is set to the 3-state mode and
OP2B is
set to a logic 1 when MCR[3] is set to a logic 0.
When 16/
68 pin is at logic 0, this output is not used.
IOR/V
DD
19 14 I When 16/68 pin is at logic 1, this input becomes the read strobe (active LOW).
When 16/
68 pin is at logic 0, this input pin is not used and should be connected
to V
DD
.
IOW/R/W 15 12 I When 16/68 pin is at logic 1 or unconnected, this input becomes the write
strobe (active LOW).
When 16/
68 pin is at logic 0, this input becomes read strobe when it is at logic
HIGH, and write strobe when it is at logic LOW.
OP2A 32 - O Output 2 (user-defined). This function is associated with individual channels,
A through B. The state at these pin(s) are defined by the user and through MCR
register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when
MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and
OP2 to a
logic 1 when MCR[3] is set to a logic 0 (see
Table 21 “Modem Control Register
bits description”, bit 3). Since these bits control both the INTA, INTB operation
and
OP2 outputs, only one function should be used at one time, INT or OP2.
OP2B 9 - O
RESET/
RESET
36 24 I Master Reset. When 16/
68 pin is at logic 1 or unconnected, this input becomes
the RESET pin (active HIGH).
When 16/
68 pin is at logic LOW, this input pin becomes RESET (active LOW).
(See
Section 7.23 “SC16C852 external reset condition and software reset” for
initialization details.)
RIA 41 - I Ring Indicator (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt if modem status interrupt is enabled.
RIB 21 - I
RTSA 33 23 O Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the
RTSx pin indicates the
transmitter has data ready and waiting to send. Writing a logic 1 in the modem
control register MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset this pin will be set to a logic 1.
RTSB 22 15 O
RXA 5 4 I Receive data A, B. These inputs are associated with individual serial channel
data to the SC16C852 receive input circuits, A through B. The RX signal will be
a logic 1 during reset, idle (no data), or when not receiving data. During the
local loopback mode, the RXA/RXB input pin is disabled and TX data is
connected to the UART RX input, internally.
RXB 4 3 I
RXRDYA31 - O Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B).
RXRDY is primarily intended for
monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive ready status
with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not
been reached. This signal can also be used for single mode transfers (DMA
mode 0).
RXRDYB 18 - O
Table 2. Pin description
…continued
Symbol Pin Type Description
LQFP48 HVQFN32
