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SC16C852IBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 37 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
[1] For 32-byte FIFO mode, refer to Section 7.3.
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 29 shows FLWCNTH register
bit settings; see Section 6.5.
[1] For 32-byte FIFO mode, refer to Section 7.3.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 30 shows FLWCNTL register bit
settings; see Section 6.5.
[1] For 32-byte FIFO mode, refer to Section 7.3.
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 29. FLWCNTH register bits description
Bit Symbol Description
7:0 FLWCNTH[7:0] This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 30. FLWCNTL register bits description
Bit Symbol Description
7:0 FLWCNTL[7:0] This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 31. Clock Prescaler register bits description
Bit Symbol Description
7:4 CLKPRES[7:4] reserved
3:0 CLKPRES[3:0] Clock Prescaler value. Reset to 0.
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 38 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.20 RS-485 turn-around time delay (RS485TIME)
The value in this register controls the turn-around time of the external line transceiver in
bit time. In automatic 9-bit mode RTSA/RTSB or DTRA/DTRB pin is used to control the
direction of the line driver, after the last bit of data has been shifted out of the transmit shift
register the UART will count down the value in this register. When the count value reaches
zero, the UART will assert RTSA/RTSB or DTRA/DTRB pin (logic 0) to turn the external
RS-485 transceiver around for receiving.
7.21 Advanced Feature Control Register 2 (AFCR2)
Table 32. RS-485 programmable turn-around time register bits description
Bit Symbol Description
7:0 RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value
represents the bit time at the programmed baud rate.
Table 33. Advanced Feature Control Register 2 register bits description
Bit Symbol Description
7:6 AFCR2[7:6] reserved
5 AFCR2[5] RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode.
logic
logic 0 = RTS or DTR is set to 0 by the UART during transmission,
and to 1 during reception
logic 1 = RTS or DTR is set to 1 by the UART during transmission,
and to 0 during reception
4 AFCR2[4] RTSCon. Enable the transmitter to control
RTSx or DTRx pin in
automatic 9-bit mode.
logic
logic 0 = transmitter does not control
RTSx or DTRx pin
logic 1 = transmitter controls
RTSx or DTRx pin
3 AFCR2[3] RS485 RTS/DTR. Select
RTSx or DTRx pin to control the external
transceiver.
logic
logic 0 =
RTSx pin is used to control the external transceiver
logic 1 = DTRx pin is used to control the external transceiver
2 AFCR2[2] TXDisable. Disable transmitter
logic 0 = transmitter is enabled
logic 1 = transmitter is disable
1 AFCR2[1] RXDisable. Disable receiver
logic 0 = receiver is enabled
logic 1 = receiver is disable
0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode
logic
logic 0 = normal RS-232 mode
logic 1 = enable 9-bit mode
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 39 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.22 Advanced Feature Control Register 1 (AFCR1)
[1] It takes 4 XTAL1 clocks to reset the device.
Table 34. Advanced Feature Control Register 1 register bits description
Bit Symbol Description
7 AFCR1[7] Concurrent write. When this bit is set the host can write concurrently to
the same register of all channel.
logic
logic 0 = Normal operation
logic 1 = Concurrent Write operation
6:5 AFCR1[6:5] reserved
4 AFCR1[4] Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
logic 0 = RX input is level-sensitive. If RXA/RXB pin is LOW, the UART
will not go to sleep. Once the UART is in Sleep mode, it will wake up if
RXA/RXB pin goes LOW.
logic 1 = RX input is edge-sensitive. UART will go to sleep even if
RXA/RXB pin is LOW, and will wake up when RXA/RXB pin toggles.
3 AFCR1[3] reserved
2 AFCR1[2] RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
logic 0 = RTS and CTS signals are used for hardware flow control.
logic 1 = DTR and DSR signals are used for hardware flow control.
RTS and CTS retain their functionality.
1 AFCR1[1] SReset. Software Reset
A write to this bit will reset the UART. Once the UART is reset this bit is
automatically set to 0.
[1]
0 AFCR1[0] TSR Interrupt. Select TSR interrupt mode
logic 0 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level, or becomes empty and the last stop bit has
been shifted out of the Transmit Shift Register.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

SC16C852IBS,157

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Buy SC16C852IBS,157
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32HVQFN
Lifecycle:
New from this manufacturer.
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