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SC16C852IBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 46 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Fig 14. Modem input/output timing in 16 mode
t
d(IOW-Q)
change of state
t
d(modem-INT)
t
d(IOR-INTL)
002aac611
change of state
change of state change of state
active
active active active
active active active
change of state
RTSA, RTSB
DTRA, DTRB
IOW
CDA, CDB
CTSA, CTSB
DSRA, DSRB
INT
IOR
RIA, RIB
t
d(modem-INT)
t
d(modem-INT)
(1) CS timing during a write cycle. See Figure 10.
(2) CS timing during a read cycle. See Figure 12.
Fig 15. Modem input/output timing in 68 mode
t
d(CS-Q)W
change of state
t
d(modem-IRQL)
t
d(modem-IRQL)
t
d(CS-IRQH)R
002aac618
t
d(modem-IRQL)
change of state
change of state change of state
active
active active active
active active active
change of state
RTSA, RTSB
DTRA, DTRB
CS (write)
(1)
CDA, CDB
CTSA, CTSB
DSRA, DSRB
IRQ
CS (read)
(2)
RIA, RIB
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 47 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
(1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8).
(2) INT is cleared when RX FIFO drops below trigger level.
Fig 16. Receive timing in 16 mode
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aac612
RXA, RXB
INT
(1)(2)
IOR
t
d(IOR-INTL)
t
d(stop-INT)
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next data
start
bit
(1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see Section 6.8).
(2) IRQ is cleared when RX FIFO drops below trigger level.
Fig 17. Receive timing in 68 mode
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aac619
t
d(CS-IRQH)R
next data
start
bit
stop
bit
parity
bit
start
bit
t
d(stop-IRQL)
RXA, RXB
IRQ
(1)(2)
CS (read)
data bits (0 to 7)
5 data bits
6 data bits
7 data bits
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 48 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Fig 18. Receive ready timing in non-FIFO mode (16 mode)
D0 D1 D2 D3 D4 D5 D6 D7
002aac613
next data
start
bit
stop
bit
parity
bit
t
d(stop-RXRDY)
RXA, RXB
RXRDYA, RXRDYB
IOR
active data
ready
start
bit
data bits (0 to 7)
active
t
d(IOR-RXRDYH)
Fig 19. Receive ready timing in non-FIFO mode (68 mode)
D0 D1 D2 D3 D4 D5 D6 D7
002aac620
next data
start
bit
stop
bit
parity
bit
t
d(stop-RXRDY)
RXA, RXB
RXRDYA, RXRDYB
CS (read)
active data
ready
start
bit
data bits (0 to 7)
active
t
d(CS-RXRDYH)R
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

SC16C852IBS,157

Mfr. #:
Buy SC16C852IBS,157
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32HVQFN
Lifecycle:
New from this manufacturer.
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