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SC16C852IBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 13 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
6.4 FIFO operation
6.4.1 32-byte FIFO mode
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are
set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward
compatible to the SC16C652B (see Table 6), and the FIFO sizes are 32 entries. The
transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).
It should be noted that the user can set the transmit trigger levels by writing to the FCR,
but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section
includes a time-out function to ensure data is delivered to the external CPU (see
Section 6.8). Please refer to Table 13 and Table 14 for the setting of FCR[7:4].
6.4.2 128-byte FIFO mode
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contains any value other than 0x00, the transmit and receive trigger levels are
set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the
transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128
with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive
trigger levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C852 monitors the
CTSA/CTSB pin for a remote buffer overflow indication and controls the RTSA/RTSB pin
for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6]
(RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1
indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]),
and the SC16C852 will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTSx input returns to a
logic 0, indicating more data may be sent.
When AFCR1[2] is set to logic 1 then the function of CTSA/CTSB pin is mapped to the
DSRA/DSRB pin, and the function of RTSA/RTSB is mapped to DTRA/DTRB pin. DSRx
and DTRx pins will behave as described above for CTS and RTS.
Table 6. Interrupt trigger level and flow control mechanism
FCR[7:6] FCR[5:4] INTA/INTB pin activation Negate RTS or
send Xoff
Assert RTS or
send Xon
RX TX
00 00 8 16 8 0
01 01 16 8 16 7
10 10 24 24 24 15
11 11 28 30 28 23
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 14 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not
be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.
However, the RTSx (or DTRx) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16C852 will continue to accept data until the receive FIFO is
full.
When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature
register set’ are all zeroes, the hardware and software flow control trigger levels are set by
FCR[7:4]; see Table 6.
When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contain any value other than 0x00, the hardware and software flow control
trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines
how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is
sent. The content in FLWCNTL determines how many bytes are in the receive FIFO
before RTS (or DTR) is asserted, or Xon is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met, spurious operation of the device might occur. When using
FLWCNTH and FLWCNTL, these registers must be initialized to proper values before
hardware or software flow control is enabled via the EFR register.
6.6 Software flow control
When software flow control is enabled, the SC16C852 compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C852 will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C852 will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C852 will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions (see Table 26). When double 8-bit Xon/Xoff characters are selected, the
SC16C852 compares two consecutive receive characters with two software flow control
8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under
the above described flow control mechanisms, flow control characters are not placed
(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters
cannot be used for data transfer.
In the event that the receive buffer is overfilling, the SC16C852 automatically sends an
Xoff character (when enabled) via the serial TX output to the remote UART. The
SC16C852 sends the Xoff1/Xoff2 characters as soon as the number of received data in
SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 15 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
the receive FIFO passes the programmed trigger level. To clear this condition, the
SC16C852 will transmit the programmed Xon1/Xon2 characters as soon as the number of
characters in the receive FIFO drops below the programmed trigger level.
6.7 Special character detect
A special character detect feature is provided to detect an 8-bit character when EFR[5] is
set. When an 8-bit character is detected, it will be placed on the user-accessible data
stack along with normal incoming RX data. This condition is selected in conjunction with
EFR[3:0] (see Table 26). Note that software flow control should be turned off when using
this special mode by setting EFR[3:0] to all zeroes.
The SC16C852 compares each incoming receive character with Xoff2 data. If a match
occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 10 “SC16C852 internal registers” shows
Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits
is dependent on the programmed word length. Line Control Register bits LCR[1:0] define
the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determines the number of bits that will be used for the special
character comparison. Bit 0 in Xon1, Xon2, Xoff1, Xoff2 corresponds with the LSB bit for
the received character.
6.8 Interrupt priority and time-out interrupts
The interrupts are enabled by IER[7:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C852
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR indicates the current singular highest priority interrupt
only. A condition can exist where a higher priority interrupt masks the lower priority
interrupt(s) (see Table 15). Only after servicing the higher pending interrupt will the lower
priority interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
Receive Data Ready and Receive Time-Out have the same interrupt priority (when
enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver
issues an interrupt after the number of characters have reached the programmed trigger
level. In this case, the SC16C852 FIFO may hold more characters than the programmed
trigger level. Following the removal of a data byte, the user should re-check LSR[0] to see
if there are any additional characters. A Receive Time-Out will not occur if the receive
FIFO is empty. The time-out counter is reset at the center of each stop bit received or
each time the Receive Holding Register (RHR) is read. The actual time-out value is
4 character time, including data information length, start bit, parity bit, and the size of stop
bit, that is, 1×, 1.5×, or 2× bit times.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

SC16C852IBS,157

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Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32HVQFN
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