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SC16C852_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 31 August 2009 24 of 60
NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
[1] The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2] Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
[3] This bit is only accessible when EFR[4] is set.
[4] Baud rate registers accessible only when LCR[7] is logic 1.
[5] Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[6] Enhanced feature register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
[7] First extra feature register set is only accessible when EFCR[2:1] = 01b.
[8] Second extra feature register set is only accessible when EFCR[2:1] = 10b.
Enhanced feature register set
[6]
0 1 0 EFR 00 Auto CTS Auto RTS special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3 TX,
RX Control
Cont-2 TX,
RX Control
Cont-1 TX,
RX Control
Cont-0 TX,
RX Control
R/W
1 0 0 Xon1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 1 Xon2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
1 1 0 Xoff1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 Xoff2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
First extra feature register set
[7]
0 1 0 TXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 0 RXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 FLWCNTH 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 FLWCNTL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Second extra feature register set
[8]
0 1 0 CLKPRES reserved reserved reserved reserved bit 3 bit 2 bit 1 bit 0 R/W
1 0 0 RS485TIME 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 AFCR2 0x00 reserved reserved RS485 RTS
Invert
Auto RS485
RTS
RS485
RTS/DTR
Transmitter
Disable
Receiver
Disable
9-bit Enable R/W
1 1 1 AFCR1 0x00 Concurrent
Write
reserved reserved Sleep
RXLow
reserved RTS/CTS
mapped to
DTR/DSR
Software
Reset
TSR
Interrupt
R/W
Table 10. SC16C852 internal registers
…continued
A2 A1 A0 Register Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
