NXP Semiconductors
SC16C852
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 31 August 2009
Document identifier: SC16C852_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Functional description . . . . . . . . . . . . . . . . . . 10
6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . 11
6.2 Extended mode (128-byte FIFO) . . . . . . . . . . 11
6.3 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 12
6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4.1 32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 13
6.4.2 128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . 13
6.5 Hardware flow control. . . . . . . . . . . . . . . . . . . 13
6.6 Software flow control . . . . . . . . . . . . . . . . . . . 14
6.7 Special character detect . . . . . . . . . . . . . . . . . 15
6.8 Interrupt priority and time-out interrupts . . . . . 15
6.9 Programmable baud rate generator . . . . . . . . 16
6.10 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 18
6.11 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 18
6.12 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.12.1 Conditions to enter Sleep mode . . . . . . . . . . . 20
6.12.2 Conditions to resume normal operation . . . . . 20
6.13 Low power feature . . . . . . . . . . . . . . . . . . . . . 20
6.14 RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 21
6.14.1 Auto RS-485
RTS control . . . . . . . . . . . . . . . . 21
6.14.2 RS-485
RTS inversion . . . . . . . . . . . . . . . . . . 21
6.14.3 Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 21
6.14.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 21
6.14.3.2 Auto address detection . . . . . . . . . . . . . . . . . . 22
7 Register descriptions . . . . . . . . . . . . . . . . . . . 22
7.1 Transmit (THR) and Receive (RHR) Holding
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 25
7.2.1 IER versus Transmit/Receive FIFO interrupt
mode operation. . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 IER versus Receive/Transmit FIFO polled
mode operation. . . . . . . . . . . . . . . . . . . . . . . . 26
7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 27
7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.1.1 Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 27
7.3.1.2 Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 27
7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 29
7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 30
7.6 Modem Control Register (MCR) . . . . . . . . . . . 31
7.7 Line Status Register (LSR) . . . . . . . . . . . . . . 32
7.8 Modem Status Register (MSR) . . . . . . . . . . . 33
7.9 Extra Feature Control Register (EFCR) . . . . . 34
7.10 Scratchpad Register (SPR) . . . . . . . . . . . . . . 34
7.11 Division Latch (DLL and DLM) . . . . . . . . . . . . 34
7.12 Transmit FIFO Level Count (TXLVLCNT) . . . . 34
7.13 Receive FIFO Level Count (RXLVLCNT) . . . . 34
7.14 Enhanced Feature Register (EFR). . . . . . . . . 35
7.15 Transmit Interrupt Level register (TXINTLVL). 36
7.16 Receive Interrupt Level register (RXINTLVL) . 36
7.17 Flow Control Trigger Level High (FLWCNTH). 37
7.18 Flow Control Trigger Level Low (FLWCNTL) . 37
7.19 Clock Prescaler (CLKPRES) . . . . . . . . . . . . . 37
7.20 RS-485 turn-around time delay (RS485TIME) 38
7.21 Advanced Feature Control Register 2
(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.22 Advanced Feature Control Register 1
(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.23 SC16C852 external reset condition and
software reset. . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41
9 Static characteristics . . . . . . . . . . . . . . . . . . . 41
10 Dynamic characteristics. . . . . . . . . . . . . . . . . 42
10.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 44
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54
12 Soldering of SMD packages . . . . . . . . . . . . . . 56
12.1 Introduction to soldering. . . . . . . . . . . . . . . . . 56
12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 56
12.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 56
12.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 57
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 58
15 Legal information . . . . . . . . . . . . . . . . . . . . . . 59
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 59
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16 Contact information . . . . . . . . . . . . . . . . . . . . 59
17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60