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AD1940YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
SigmaDSP Multichannel
28-Bit Audio Processor
AD1940/AD1941
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved.
FEATURES
16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully programmable program RAM for custom
program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter
updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic
parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × f
S
, 256 × f
S
, 384 × f
S
, or
512 × f
S
clocks
Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio
delay at f
s
= 48 kHz
Flexible serial data port with I
2
S-compatible, left-justified,
and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and
5 V systems
Programmable low power mode
Fast start-up and boot time from power-on or reset
48-lead LQFP plastic package
APPLICATIONS
Automotive sound systems
Digital televisions
Home theater systems (Dolby digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)
FUNCTIONAL BLOCK DIAGRAM
VOLTAGE
REGULATOR
AD1940/AD1941
28 × 28
DSP CORE
DATA FORMAT:
PLL
SERIAL
CONTROL
INTERFACE
SERIAL DATA/
TDM INPUTS
MASTER
CLOCK
INPUT
SPI/I
2
C I/O
RAM ROM
SERIAL
DATA/
TDM
OUTPUTS
04607-0-001
2
4
4
2
2
5.23 (SINGLE
PRECISION)
10.46 (DOUBLE
PRECISION)
Figure 1.
GENERAL DESCRIPTION
The AD1940/AD1941 are a complete 28-bit, single-chip, multi-
channel audio SigmaDSP
™ for equalization, multiband dynamic
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compen-
sate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940/AD1941 is
comparable to that found in high end studio equipment. Most
of the processing is done in full, 56-bit double-precision mode,
resulting in very good, low level signal performance and the
absence of limit cycles or idle tones. The dynamics processor
uses a sophisticated, multiple-breakpoint algorithm often found
in high end broadcast compressors.
The AD1940/AD1941 are a fully programmable DSP. Easy to
use software allows the user to graphically configure a custom
signal processing flow using blocks such as biquad filters, dyna-
mics processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1940/AD1941’s digital input and output ports allow a
glueless connection to ADCs and DACs by multiple, 2-channel
serial data streams or TDM data streams. When in TDM mode,
the AD1940/AD1941 can input 8 or 16 channels of serial data,
and can output 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1940
is controlled by a 4-wire SPI
® port; the AD1941 is controlled by
a 2-wire I
2
C® bus. Other than the control interface, the
functions of the two parts are identical.
AD1940/AD1941
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Digital I/O ..................................................................................... 3
Power .............................................................................................. 3
Digital Timing ............................................................................... 4
PLL ................................................................................................. 5
Regulator ........................................................................................ 5
Temperature Range ...................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Digital Timing Diagrams ................................................................. 7
Pin Configuration and Function Descriptions ............................. 9
Features ............................................................................................ 11
Pin Functions .............................................................................. 12
Signal Processing ............................................................................ 14
Overview ...................................................................................... 14
Numeric Formats ........................................................................ 14
Programming .............................................................................. 14
Control Port ..................................................................................... 15
Overview ...................................................................................... 15
AD1940 SPI Port ........................................................................ 15
AD1941 I
2
C Port ......................................................................... 15
RAMs and Registers ....................................................................... 19
Control Port Addressing ........................................................... 19
Parameter RAM Contents ......................................................... 19
Recommended Program/Parameter Loading Procedures .... 20
Target/ Slew RAM ....................................................................... 20
Safeload Registers ....................................................................... 23
Data Capture Registers .............................................................. 23
DSP Core Control Register ....................................................... 24
RAM Configuration Register ................................................... 25
Control Port Read/Write Data Formats .................................. 25
Serial Data Input/Output Ports .................................................... 28
Serial Output Control Registers ............................................... 30
Serial Input Control Register .................................................... 30
Initialization .................................................................................... 33
Power-Up Sequence ................................................................... 33
Setting Master Clock/PLL Mode .............................................. 33
Volt age Regu lator ....................................................................... 33
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
4/10—Rev. A to Rev. B
Changes to Voltage Regulator Section ..................................... 34
Updated Outline Dimensions ................................................... 35
Changes to Ordering Guide ...................................................... 35
4/05—Rev. 0 to Rev. A
Added AD1941 .............................................................. Universal
Changes to Specifications ............................................................ 3
Changes to Pin Function Descriptions ...................................... 9
Changes to Features Section...................................................... 11
Changes to Pin Functions Section ............................................ 13
Addition of AD1940 SPI Port Section ..................................... 15
Added Table 13 to Table 16 ....................................................... 18
7/04—Revision 0: Initial Version
AD1940/AD1941
Rev. B | Page 3 of 36
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter Conditions
Supply Voltage (VDD) 2.5 V
PLL Voltage (PLL_VDD) 2.5 V
Output Voltage (ODVDD) 5.0 V
INVDD Voltage 5.0 V
Ambient Temperature 25°C
Master Clock Input 3.072 MHz, 64 × f
s
mode
Load Capacitance 50 pF
Load Current ±1 mA
Input Voltage, HI 2.4 V
Input Voltage, LO 0.8 V
DIGITAL I/O
VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case).
Table 2.
Parameter Comments Min Max Unit
Input Voltage, HI (V
IH
) 2.1 V
Input Voltage, LO (V
IL
) 0.8 V
Input Leakage (I
IH
) 10 μA
Input Leakage (I
IL
) 10 μA
High Level Output Voltage (V
OH
) ODVDD = 4.5 V, I
OH
= 1 mA 3.9 V
High Level Output Voltage (V
OH
) ODVDD = 3.0 V, I
OH
= 1 mA 2.6 V
Low Level Output Voltage (V
OL
) ODVDD = 4.5 V, I
OL
= 1 mA
1
0.4 V
Low Level Output Voltage (V
OL
) ODVDD = 3.0 V, I
OL
= 1 mA
1
0.3 V
Input Capacitance 5 pF
1
SDA is measured with a 3 mA sink current.
POWER
Table 3.
Parameter Min Typ Max
1
Unit
SUPPLIES
Voltage 2.25 2.5 2.75 V
Digital Current 92 155
2
mA
PLL Current 3.5 8 mA
Digital Current, Reset 4.5
3
13
3
mA
PLL Current, Reset 3 8.5 mA
DISSIPATION
Operation, All Supplies 238.8 mW
Reset, All Supplies 10.8 mW
1
Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.
2
Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ.
3
The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.
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AD1940YSTZ

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Manufacturer:
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Description:
Audio DSPs IC 28-Bit Audio Processor
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