AD1940/AD1941
Rev. B | Page 15 of 36
CONTROL PORT
OVERVIEW
The AD1940/AD1941 have many different control options that
can be set through an SPI or I
2
C interface. The AD1940 uses a
4-wire SPI control port and the AD1941 uses a 2-wire I
2
C bus
control port. Most signal processing parameters are controlled
by writing new values to the parameter RAM using the control
port. Other functions, such as mute and input/output mode
control, are programmed by writing to the control registers.
The control port is capable of full read/write operation for all of
the memories and registers. All addresses may be accessed in
both a single-address mode or a burst mode. A control word
consists of the chip address, the register/RAM subaddress, and
the data to be written. The number of bytes per word depends
on the type of data that is written.
The first byte of a control word (Byte 0) contains the 7-bit chip
address plus the R/W bit. The next two bytes (Bytes 1 and 2)
form the subaddress of the memory or register location within
the AD1940/AD1941. This subaddress needs to be two bytes
because the memories within the AD1940/AD1941 are directly
addressable, and their sizes exceed the range of single-byte
addressing. All subsequent bytes (Bytes 3, 4, etc.) contain the
data, such as control port, program, or parameter data.
The exact formats for specific types of writes are shown in Table
26 to Table 35.
The AD1940/AD1941 have several mechanisms for updating
signal processing parameters in real time without causing pops
or clicks. In cases where large blocks of data need to be down-
loaded, the output of the DSP core can be halted (using Bit 9 of
the core control register), new data loaded, and then restarted.
This is typically done during the booting sequence at start-up or
when loading a new program into RAM. In cases where only a
few parameters need to be changed, they can be loaded without
halting the program. To avoid unwanted side effects while
loading parameters on the fly, the SigmaDSP provides the
safeload registers. The safeload registers can be used to buffer a
full set of parameters (for example, the five coefficients of a
biquad) and then transfer these parameters into the active
program within one audio frame. The safeload mode uses
internal logic to prevent contention between the DSP core and
the control port.
AD1940 SPI PORT
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the AD1940/AD1941 on
the falling edge of CCLK and should be clocked into the
receiving device, such as a microcontroller, on CCLK’s rising
edge. The CDATA signal carries the serial input data and the
COUT signal is the serial output data. The COUT signal
remains three-stated until a read operation is requested. This
allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions follow the same basic format,
shown in Tabl e 11. A timing diagram is shown in Figure 4. All
data written should be MSB first.
Table 11. Generic SPI Word Format
Byte 0 Byte 1 Byte 2 Byte 3
Byte 4,
etc.
chip_adr [6:0],
R/
W
0000,
subadr
[11:8]
subadr [7:0] Data Data
Chip Address R/
W
The first byte of an SPI transaction includes the 7-bit chip
address and a R/
W
bit. The chip address is set by the ADR_SEL
pin. This allows two AD1940s to share a CLATCH signal, yet
operate independently. When ADR_SEL is low, the chip address
is 0000000; when it is high, the address is 0000001. The LSB of
this first byte determines whether the SPI transaction is a read
(Logic Level 1) or a write (Logic Level 0).
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format diagram for continuous mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 11. A sample timing
diagram of a single SPI read operation is shown in Figure 12.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Bytes 0 to 2 contain the addresses and
R/W bit, and subsequent bytes carry the data.
AD1941 I
2
C PORT
The AD1941 supports a 2-wire serial (I
2
C-compatible) micro-
processor bus driving multiple peripherals. Two pins, serial data
(SDA) and serial clock (SCL), carry information between the
AD1941 and the system I
2
C master controller. The AD1941 is
always a slave on the I
2
C bus, which means that it never initiates
a data transfer. Each slave device is recognized by a unique
address. The AD1941 has four possible slave addresses, two for
writing operations and two for reading. These are unique
addresses for the device and are illustrated in Table 12. The LSB
