AD1940/AD1941
Rev. B | Page 12 of 36
PIN FUNCTIONS
Table 1 0 shows the AD1940/AD1941’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by
writing to Bits 2:0 of the serial input port control register.
SDATA_IN2 and SDATA_IN3 are dual-function pins that can
be set to a variety of standard 2-channel formats or to TDM
mode. Two of these four pins (SDATA_IN2 and SDATA_IN3)
can be used as TDM inputs in either dual-wire 8-channel mode
or single-wire 16-channel mode (TDM_O0 only). In dual-wire
8-channel mode, Channels 0 to 7 are input on SDATA_IN3 and
Channels 8 to 15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0 to 15 are input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0 through
SDATA_IN3 signals. The input port is always in a slave
configuration. These pins also function as frame sync and bit
clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard 2-channel formats. They are grouped into two groups
of four pins (Pins 0 to 3 and Pins 4 to 7); each group can be
independently set to any of the available serial modes, allowing
the AD1940/AD1941 to simultaneously communicate with two
external devices with different serial formats. Two of these eight
pins (SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire 16-
channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0 to 7 are output on SDATA_OUT0 and
Channels 8 to 15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0 through SDATA_OUT3. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4 through SDATA_OUT7. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
MCLK
Master Clock Input. The AD1940/AD1941 uses a PLL to
generate the appropriate internal clock for the DSP core. An
in-depth description of using the PLL is found in the Setting
Master Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
CDATA (AD1940)
Serial Data Input for the SPI Control Port.
COUT (AD1940)
Serial Data Output for the SPI Port. This is used for reading
back registers and memory locations. It is three-stated when an
SPI read is not active.
CCLK (AD1940)
SPI Bit Clock. This clock may either run continuously or be
gated off between SPI transactions.
CLATCH (AD1940)
SPI Latch Signal. This must go low at the beginning of an SPI
transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction.
SCL (AD1941)
I
2
C Clock. This pin is always an input because the AD1941
cannot act as a master on the I
2
C bus. The line connected to this
pin should have a 2 kΩ pull-up resistor on it.
SDA (AD1941)
I
2
C Serial Data. The data line is bidirectional. The line
connected to this pin should have a 2 kΩ pull-up resistor on it.
