AD1940/AD1941
Rev. B | Page 25 of 36
Initialize Data Memory with Zeros (Bit 7)
Setting this bit to 1 initializes all data memory locations to 0.
This bit is cleared to 0 after the operation is complete. This bit
should be asserted after a complete program/parameter
download has occurred to ensure click-free operation.
Zero Serial Input Port (Bit 6)
When this bit is set to 1, the 16 serial input channels are forced
to all 0s.
Initiate Safe Transfer to Target RAM (Bit 5)
Setting this bit to 1 initiates a safeload transfer to the target/slew
RAM. This bit clears when the operation is completed. Of five
safeload register pairs (address/data), only those registers that
have been written since the last safeload event are transferred.
Address 0 corresponds to the first target RAM location.
Initiate Safe Transfer to Parameter RAM (Bit 4)
Setting this bit to 1 initiates a safeload transfer to the parameter
RAM. This bit clears when the operation is completed. Of five
safeload registers pairs (address/data), only those registers that
have been written since the last safeload event are transferred.
Address 0 corresponds to the first parameter RAM location.
Input Serial Port to Sequencer Sync (Bits 3:2)
Normally, the internal sequencer is synchronized to the
incoming audio frame rate by comparing the internal program
counter with the edge of the LRCLK input signal. In some cases
the AD1940/AD1941 may be used to decimate an incoming
signal by some integer factor. In this case, it is desirable to
synchronize the sequencer to a submultiple of the incoming
LRCLK rate so more than one audio input sample is available to
the program during a single audio output frame. For example, if
these bits are set to 01 (LRCLK/2), a 96 kHz input can be used
with a 48 kHz output, allowing two consecutive input samples
to be processed during a single audio output frame. Operation
in this mode may require custom assembly language coding in
the ADI graphical tools.
Program Length (Bits 1:0)
96 kHz and 192 kHz Modes
These bits set the length of the internal program. The default
program length is 1,536 instructions for f
S
= 48 kHz, but the
program length can be shortened by factors of 2 to accom-
modate sample rates higher than 48 kHz. For f
S
= 96 kHz, the
program length should be set to 768 (01). For f
S
= 192 kHz, the
program length should be set to 384 steps (10). A program
length of 192 steps is available, but is not commonly used.
Low Power Mode
This setting can also be used to reduce the power consumption
of the AD1940/AD1941. If the program length is set to
768 steps and f
S
= 48 kHz instead of 96 kHz, then the power
consumption of the part is cut approximately in half.
Correspondingly, when the program length is set to 384 steps
with f
S
= 48 kHz, the power consumption is about ¼ of
what it is in normal operation with 1,536 program steps and
f
S
= 48 kHz.
Table 25. RAM Configuration Register (2643)
Register Bits Function
7:4 Reserved
3:0
RAM modulo, 1 LSB corresponds to
512 locations, max = 0b1100 (6 k words)
RAM CONFIGURATION REGISTER
The AD1940/AD1941 use a modulo RAM addressing scheme
to allow filters and other blocks to be coded easily without
requiring filter data to be explicitly moved during the filtering
operation. This is accomplished by adding the contents of an
address offset counter to the actual base address supplied in the
AD1940/AD1941’s cores. This address offset counter is incre-
mented automatically at the audio frame rate.
This method works well for most audio applications that
involve filtering. In some cases, however, it is desirable to have
direct access to the RAM, bypassing the autoincrementing
address offset counter. For this reason, the data memories in the
AD1940/AD1941 can be divided into modulo and nonmodulo
portions by programming the RAM configuration register
(Table 25). The address range from 0 to 512 × (RAM config-
uration register contents) is treated as modulo memory with
autoincrementing address offset registers. The maximum
setting of this register is the full size of the RAM, or 6,144 (6 k
words) data words. Note that addresses in this range
automatically wrap around the modulo boundary as set by the
register. This feature is not normally used with ADI supplied
blocks. For normal operation, this register may be left in its
default state, which sets up the entire RAM to use the
autoincrement feature. This feature is included for maximum
programming flexibility and may be used in the case of special
software development.
CONTROL PORT READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to be
byte oriented. This allows easy programming of common
microcontroller chips. In order to fit into a byte-oriented
format, 0s are appended to the data fields before the MSB in
order to extend the data word to the next multiple of eight bits.
For example, 28-bit words written to the parameter RAM are
appended with four leading 0s to reach 32 bits (four bytes);
40-bit words written to the program RAM are not appended
with any 0s because it is already a full 5 bytes. These zero
extended data fields are appended to a 3-byte field consisting of
a 7-bit chip address, a read/write bit, and an 11-bit RAM/
register address. The control port knows how many data bytes
to expect based on the address that is received in the first three
bytes.
