AD1940/AD1941
Rev. B | Page 33 of 36
INITIALIZATION
POWER-UP SEQUENCE
The AD1940/AD1941 have a built-in power-up sequence that
initializes the contents of all internal RAMs. During this time,
the contents of the internal program boot ROM are copied to
the internal program RAM memory and the parameter RAM
(all 0s) is filled with values from its associated boot ROM. The
default boot ROM program simply copies the serial inputs to
the serial outputs with no processing. The data memories are
also cleared during this time.
The boot sequence, which starts on the rising edge of the
RESETB pin, lasts for 8,192 cycles of the signal on the MCLK
pin at start-up. Assuming even the slowest possible signal on
this pin, a 64 × f
S
clock, the boot sequence still completes before
the PLL locks to the input clock. Since the boot sequence
requires a stable master clock, the user should avoid writing to
or reading from the registers until the MCLK input signal has
settled and the PLL has locked. The PLL takes approximately
3 ms to lock. Coming out of reset, the clock mode is imme-
diately set by the PLL_CTRL0, PLL_CTRL1, and PLL_CTRL2
pins. Reset is synched to the falling edge of the internal MCLK.
The power-up default signal processing flow in the AD1940/
AD1941 simply takes the eight inputs and copies these signals
to the 16 digital outputs, as shown in Figure 28.
04607-0-004
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
Figure 28. Default Program Signal Flow
SETTING MASTER CLOCK/PLL MODE
The AD1940/AD1941’s MCLK input feeds a PLL, which gen-
erates the 1536 × f
S
clock to run the DSP core. In normal
operation, the input to MCLK must be one of the following;
64 × f
S
, 256 × f
S
, 384 × f
S
, or 512 × f
S
, where f
S
is the input
sampling rate. The mode is set on PLL_CTRL0, PLL_CTRL1,
and PLL_CTRL2, according to Table 4 1. If the
AD1940/AD1941 are set to receive double-rate signals (by
reducing the number of program steps/sample by a factor of 2
using the core control register), then the master clock
frequencies must be either 32 × f
S
, 128 × f
S
, 192 × f
S
, or 256 × f
S
.
If the AD1940/AD1941 are set to receive quad rate signals (by
reducing the number of program steps/sample by a factor of 4
using the core control register), then the master clock
frequencies must be 16 × f
S
, 64 × f
S
, 96 × f
S
, or 128 × f
S
. On
power-up, a clock signal must be present on MCLK so that the
AD1940/AD1941 can complete their initialization routine. The
PLL can also run in bypass mode, where the clock present on
MCLK is fed directly to the
DSP core, although this setting is not recommended for
normal operation.
Table 41. PLL Modes
MCLK Input PLL_CTRL2 PLL_CTRL1 PLL_CTRL0
64 × f
S
0 0 0
256 × f
S
0 1 0
384 × f
S
X
1
X
1
1
512 × f
S
1 0 0
Bypass 1 1 0
1
X = don’t care
The clock mode should not be changed without also resetting
the AD1940/AD1941. If the mode is changed on the fly, a click
or pop may result on the outputs. The state of the PLL_CTRLx
pins should be changed while RESETB is held low.
VOLTAGE REGULATOR
The AD1940/AD1941 include an on-board voltage regulator
that allows the chip to be used in systems where a 2.5 V supply
is not available, but 3.3 V or 5 V is. The only external
components needed for this are a PNP transistor such as a
ZX5T953G, a single capacitor, and a single resistor. The
recommended design for the voltage regulator is shown in
Figure 29. The 10 μF and 100 nF capacitors shown in this
schematic are recommended for bypassing, but are not
necessary for operation. Here, VDD is the main system voltage
(3.3 V or 5 V) and should be connected to VSUPPLY. 2.5 V is
generated at the transistor’s collector, which is connected to the
VDD pins, PLL_VDD and VSENSE. The reference voltage on
VREF is 1.15 V and is generated by the regulator. A 1 nF
capacitor should be connected between this pin and ground.
VDRIVE is connected to the base of the PNP transistor. A 1 kΩ
resistor should be connected between VDRIVE and VSUPPLY.
10μF
10μF
100nF
100nF
1nF
1kΩ
AD1940/AD1941
DVDD
ZX5T953G
04607-0-009
VSUPPLY
VREF
VDRIVE
VSENSE
VDD
++
PLL_VDD
Figure 29. Voltage Regulator Design
