AD1940/AD1941
Rev. B | Page 16 of 36
of the byte sets either a read or write operation; Logic Level 1
corresponds to a read operation and Logic Level 0 corresponds
to a write operation. The seventh bit of the address is set by
tying the ADR_SEL pin of the AD1941 to Logic Level 0 or Logic
Level 1.
The AD1941 I
2
C port uses a spike filter that can be enabled or
disabled by the I2C_FILT_ENB pin. Enabling this filter guar-
antees that all isolated spikes, both positive and negative, less
than 50 ns wide are removed from the I
2
C signal. The filter is
active when the I2C_FILT_ENB pin is low and is disabled when
the pin is high. Typically, the largest spike that is filtered is
67 ns wide.
Table 12. AD1941 I
2
C Addresses
ADR_SEL R/W Slave Address
0 0 0x28
0 1 0x29
1 0 0x2A
1 1 0x2B
Addressing
Initially, all devices on the I
2
C bus are in an idle state, which is
where the devices monitor the SDA and SCL lines for a start
condition and the proper address. The I
2
C master initiates a
data transfer by establishing a start condition, defined by a
high-to-low transition on SDA while SCL remains high. This
indicates that an address/data stream will follow. All devices on
the bus respond to the start condition and read the next byte
(7-bit address + R/W bit) MSB first. The device that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The R/W bit
determines the direction of the data. A Logic 0 on the LSB of
the first byte means the master writes information to the
peripheral. A Logic 1 on the LSB of the first byte means the
master reads information from the peripheral. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 13 shows the timing of an I
2
C write.
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically if a stop condition is not
encountered after a single-word write. The registers and
memories in the AD1941 range in width from one to five bytes,
so the autoincrement feature knows the mapping between sub-
addresses and the word length of the destination register (or
memory location). A data transfer is always terminated by a
stop condition.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
AD1941 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while in
autoincrement mode, one of two actions are taken. In read
mode, the AD1941 outputs the highest subaddress register
contents until the master device issues a no-acknowledge,
indicating the end of a read. A no-acknowledge condition is
where the SDA line is not pulled low on the ninth clock pulse
on SCL. If the highest subaddress location is reached while in
write mode, the data for the invalid byte is not loaded into any
subaddress register, a no-acknowledge is issued by the AD1941
and the part returns to the idle condition.
I
2
C Read and Write Operations
Table 1 3 shows the timing of a single-word write operation.
Every ninth clock, the AD1941 issues an acknowledge by
pulling SDA low.
Table 1 4 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The AD1941 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single word read operation is shown in Table
15. Note that the first R/
W
bit is still a 0, indicating a write
opera-tion. This is because the subaddress still needs to be
written in order to set up the internal address. After the
AD1941 acknow-ledges the receipt of the subaddress, the
master must issue a repeated start command followed by the
chip address byte with the R/
W
set to 1 (read). This causes the
AD1941’s SDA to turn around and begin driving data back to
the master. The master then responds every ninth pulse with an
acknowledge pulse to the AD1941.
Table 1 6 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The AD1941 knows to increment its subaddress register
every two bytes because the requested subaddress corresponds
to a register or memory area with word lengths of two bytes.
Other address ranges may have a variety of word lengths
ranging from one to five bytes; the AD1941 always decodes the
subaddress and sets the autoincrement circuit so that the
address increments after the appropriate number of bytes.
