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AD1940YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
AD1940/AD1941
Rev. B | Page 4 of 36
DIGITAL TIMING
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 4. Digital Timing
1
Parameter Mnemonic Comments Min Max Unit
MASTER CLOCK, SERIAL DATA PORTS, RESET
MCLK Period t
MP
512 f
S
mode 36 244 ns
MCLK Period t
MP
384 f
S
mode 48 366 ns
MCLK Period t
MP
256 f
S
mode 73 488 ns
MCLK Period t
MP
64 f
S
mode 291 1953 ns
MCLK Period t
MP
Bypass mode 12 ns
MCLK Duty Cycle t
MDC
Bypass mode 40 60 %
BCLK_IN LO Pulse Width t
BIL
4 ns
BCLK_IN HI Pulse Width t
BIH
2 ns
LRCLK_IN Setup t
LIS
To BCLK_IN rising 12 ns
LRCLK_IN Hold t
LIH
From BCLK_IN rising 0 ns
SDATA_INx Setup t
SIS
To BCLK_IN rising 3 ns
SDATA_INx Hold t
SIH
From BCLK_IN rising 2 ns
LRCLK_OUTx Setup t
LOS
Slave mode 2 ns
LRCLK_OUTx Hold t
LOH
Slave mode 2 ns
BCLK_OUTx Falling to LRCLK_OUTx
Timing Skew
t
TS
2 ns
SDATA_OUTx Delay
t
SODS
Slave mode, from
BCLK_OUTx falling
17 ns
SDATA_OUTx Delay
t
SODM
Master mode, from
BCLK_OUTx falling
17 ns
RESETB LO Pulse Width t
RLPW
10 ns
SPI PORT (AD1940)
CCLK Pulse Width LO t
CCPL
1 × INTMCLK (14)
2
ns
CCLK Pulse Width HI t
CCPH
1 × INTMCLK (14)
2
ns
CLATCH Setup t
CLS
To CCLK rising 0 ns
CLATCH Hold t
CLH
From CCLK rising 2 × INTMCLK + 4 (32)
2
ns
CLATCH Pulse Width HI t
CLPH
2 × INTMCLK (28)
2
ns
CDATA Setup t
CDS
To CCLK rising 0 ns
CDATA Hold t
CDH
From CCLK rising 2 × INTMCLK + 2 (30)
2
ns
COUT Delay t
COD
From CCLK rising 4 × INTMCLK +18 (74)
2
ns
I
2
C PORT (AD1941)
SCL Clock Frequency f
SCL
400 kHz
SCL Low t
SCLL
1.3 μs
SCL High t
SCLH
0.6 μs
Setup Time (Start Condition) t
SCS
Relevent for repeated start
condition
0.6 μs
Hold Time (Start Condition) t
SCH
First clock generated after
this period
0.6 μs
Setup Time (Stop Condition) t
SSH
0.6 μs
Data Setup Time t
DS
100 ns
SDA and SCL Rise Time t
SR
300 ns
SDA and SCL Fall Time t
SF
300 ns
Bus-Free Time t
BFT
Between stop and start 1.3 μs
1
All timing specifications are given for the default (I
2
S) states of the serial input control port and the serial output control ports. See Table 37.
2
These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × f
s
, so the internal
master clock at f
s
= 48 kHz has a 14 ns period. The values in parentheses are the timing values for f
s
= 48 kHz.
AD1940/AD1941
Rev. B | Page 5 of 36
PLL
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 5.
Parameter Min Typ Max Unit
Lock Time 3 20 ms
REGULATOR
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 6.
Parameter Min Typ Max Unit
VSENSE Output Voltage 2.25 2.5 2.68 V
TEMPERATURE RANGE
Table 7.
Parameter Min Typ Max Unit
Functionality Guaranteed –40 +105 °C Ambient
–40 +125 °C Case
AD1940/AD1941
Rev. B | Page 6 of 36
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Min Max Unit
VDD to DGND –0.3 +3.0 V
PLL_ VDD to PGND –0.3 +3.0 V
OD VDD to DGND –0.3 +6.0 V
INVDD to DGND ODVDD +6.0 V
Digital Inputs DGND – 0.3 INVDD + 0.3 V
Maximum Junction
Temperature
135 °C
Storage Temperature
Range
–65 +150 °C
Soldering (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 9. Package Characteristics
Parameter Min Typ Max Unit
θ
JA
Thermal Resistance (Junction-
to-Ambient)
72 °C/W
θ
JC
Thermal Resistance (Junction-
to-Case)
19.5 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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AD1940YSTZ

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Manufacturer:
Analog Devices Inc.
Description:
Audio DSPs IC 28-Bit Audio Processor
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