AD1940/AD1941
Rev. B | Page 9 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
VDD
MCLK
RESERVED
PLL_VDD
NC
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
GND
VDD
PIN 1
INDICATOR
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
AD1940
TOP VIEW
(Not to Scale)
V
D
D
S
D
A
T
A
_
I
N
1
S
D
A
T
A
_
I
N
2
S
D
A
T
A
_
I
N
3
C
O
U
T
C
C
L
K
C
L
A
T
C
H
C
D
A
T
A
R
E
S
E
T
B
G
N
D
SDATA_IN0
ADR_SEL
GND
VREF
VDRIVE
VSENS
E
VS
UPPLY
INVDD
SDATA_
OUT7
SDATA_OU
T6
O
DVDD
SDATA_OU
T5
SD
ATA_OUT4
VDD
04607-0-002
LRCLK_IN
BCLK_IN
NC = NO CONNECT
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
VDD
MCLK
RESERVED
PLL_VDD
I2C_FILT_EN
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
GND
VDD
PIN 1
INDICATOR
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
AD1941
TOP VIEW
(Not to Scale)
VDD
SDATA
_IN1
S
DATA_IN2
SDATA_
IN3
SDA
SCL
NC
NC
RESETB
GND
SDATA_IN0
ADR_SEL
GND
VREF
VDRIVE
VSENS
E
VS
UPPLY
INVDD
SDATA_
OUT7
SDATA_OU
T6
O
DVDD
SDATA_OU
T5
SD
ATA_OUT4
VDD
04607-0-011
LRCLK_IN
BCLK_IN
NC = NO CONNECT
Figure 7. 48-Lead LQFP Pin Configuration, AD1940 Figure 8. 48-Lead LQFP Pin Configuration, AD1941
Table 10. Pin Function Descriptions
Pin No.
AD1940 AD1941 I/O Mnemonic Description
1, 25, 37 1, 25, 37 VDD Core Power.
2 2 IN MCLK Master Clock Input.
3 3 RESERVED This pin should be connected to ground.
4 4 IN PLL_CTRL0 PLL Control 0.
5 5 IN PLL_CTRL1 PLL Control 1.
6 6 IN PLL_CTRL2 PLL Control 2.
7 7 PLL_GND PLL Ground.
8 8 PLL_VDD PLL Power.
9 21, 22 NC No Connect.
9 IN I2C_FILT_ENB I
2
C Filter Enable, Active Low.
10 10 IN LRCLK_IN Left/Right Clock for Serial or TDM Data Inputs.
11 11 IN BCLK_IN Bit Clock for Serial or TDM Data Inputs.
12, 24, 36,
48
12, 24, 36,
48
GND Digital Ground.
13 13 VDD Core Power.
14 14 IN SDATA_IN0 Serial Data Input 0.
15 12 IN SDATA_IN1 Serial Data Input 1.
16 16 IN SDATA_IN2/TDM_IN1 Serial Data Input 2/TDM Input 1.
17 17 IN SDATA_IN3/TDM_IN0 Serial Data Input 3/TDM Input 0.
18 18 IN ADR_SEL Control Port Address Select.
19 OUT COUT SPI Data Output.
20 IN CCLK Clock for SPI.
21 IN CLATCH SPI Data Latch.
