Data Sheet ADE9153A
Rev. 0 | Page 27 of 50
The zero-crossing detection circuits have two different output rates:
4 kSPS and 512 kSPS. The 4 kSPS zero-crossing signal calculates
the line period, updates the ZXx bits in the status register, and
monitors the zero-crossing timeout and energy accumulation
functions. The 512 kSPS zero-crossing signal calculates the
angle and updates the zero-crossing output on the CF2/ZX/
DREADY pin.
CF1/ZX/DREADY
The CF1/ZX/DREADY pin can output zero crossings using the
ZX_OUT_OE bit in the CONFIG1 register. The CF1/ZX/
DREADY output pin goes from low to high when a negative to
positive transition is detected and from high to low when a
positive to negative transition occurs.
Zero-Crossing Timeout
If a zero crossing is not received after (ZXTOUT + 1)/4000 sec,
the ZXTOAV bit in the status register is set and generates an
interrupt on the
IRQ
pin.
Line Period Calculation
The ADE9153A calculates the line period on the voltage with the
result available in the APERIOD register. Calculate the line period,
t
L
, from the APERIOD register according to the following equation:
t
L
=
(sec)
24000
1
16
APERIOD
If the calculated period value is outside the range of 40 Hz to
70 Hz, or if zero crossings are not detected, the APERIOD register
is coerced to correspond to 50 Hz or 60 Hz, depending on the
SELFREQ bit in the ACCMODE register.
Angle Measurement
The ADE9153A provides two angle measurements: ANGL_AV_AI
for the angle between current Channel A and the voltage channel,
and ANGL_AI_BI for the angle between Current Channel A and
Current Channel B. To convert angle register readings to degrees,
use the following equations.
For a 50 Hz system,
Angle (Degrees) = ANGL_x_y × 0.017578125
For a 60 Hz system,
Angle (Degrees) = ANGL_x_y × 0.02109375
One Cycle RMS Measurement
RMS½ is an rms measurement performed over one line cycle,
updated every half cycle. This measurement is provided on all
three channels for voltage and current. All the half cycle rms
measurements are performed over the same time interval and
update at the same time, as indicated by the RMS_OC_RDY bit
in the status register. The results are stored in the AIRMS_OC,
AVRMS_OC, and BIRMS_OC registers. The xIRMS_OC and
AVRMS_OC register reading with full-scale inputs is
52,725,703 codes and 26,362,852, respectively.
It is recommended to select the data before the high-pass filter
for the fast rms measurement by setting the RMS_OC_SRC bit
in the CONFIG0 register.
The voltage channel is used for the timing of the rms½
measurement. Alternatively, set the UPERIOD_SEL bit in the
CONFIG2 register to set desired period in the USER_PERIOD
register for line period measurement. An offset correction register,
xRMS_OC_OS, is available for improved performance with
small input signal levels. The datapath is shown in Figure 53.
Dip and Swell Indication
The ADE9153A monitors the rms½ value on the voltage
channel to determine a dip and swell event. If the voltage goes
below a threshold specified in the DIP_LVL register for a user
configured number of half cycles in the DIP_CYC register, the
DIPA bit is set in the EVENT_STATUS register. The minimum
rms½ value measured during the dip is stored in the DIPA register.
Similarly, if the voltage goes above a threshold specified in the
SWELL_LVL register for a user configured number of half
cycles in the SWELL_CYC register, the SWELLA bit is set in the
EVENT_STATUS register. The maximum rms½ value measured
during the swell is stored in the SWELLA register.
The dip and swell event generates an interrupt on the
IRQ
pin.
APERIOD
USER_PERIOD
UPERIOD_SEL
xI_WAV
xIRMSONEOS
HPF
PHASE
COMP
INTEGRATOR
(ON BI ONLY)
HPFDIS INTEN_BI
RMS_OC_SEL
CURRENT
CHANNEL
SAMPLES
xIRMSONE
FAST RMS½
16258-153
Figure 53. RMS½, RMS Measurements
