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ADE9153AACPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
ADE9153A Data Sheet
Rev. 0 | Page 34 of 50
Address Name Description
Length
(Bits) Reset Access
0x40F VLEVEL
Register used in the algorithm that computes the fundamental
reactive power.
32 0x0045D450 R/W
0x410 DIP_LVL Voltage RMS_OC dip detection threshold level. 32 0x00000000 R/W
0x411 DIPA Phase A voltage RMS_OC value during a dip condition. 32 0x007FFFFF R
0x414 SWELL_LVL Voltage RMS_OC swell detection threshold level. 32 0x00FFFFFF R/W
0x415 SWELLA Phase A voltage RMS_OC value during a swell condition. 32 0x00000000 R
0x418 APERIOD Line period on the Phase A voltage. 32 0x00500000 R
0x41C ACT_NL_LVL No load threshold in the total active power datapath. 32 0x00008225 R/W
0x41D REACT_NL_LVL No load threshold in the fundamental reactive power datapath. 32 0x00008225 R/W
0x41E APP_NL_LVL No load threshold in the total apparent power datapath. 32 0x00008225 R/W
0x41F PHNOLOAD Phase no load register. 32 0x00000000 R
0x420 WTHR
Sets the maximum output rate from the digital to frequency
converter of the total active power for the CF calibration pulse
output. It is recommended to leave this at WTHR = 0x00100000.
32 0x00100000 R/W
0x421 VARTHR See WTHR. It is recommended to leave this at VARTHR = 0x00100000. 32 0x00100000 R/W
0x422 VATHR
See WTHR. It is recommended to leave this value at VATHR =
0x00100000.
32 0x00100000 R/W
0x423 LAST_DATA_32
This register holds the data read or written during the last 32-bit
transaction on the SPI port.
32 0x00000000 R
0x424 CT_PHASE_MEAS
Set to 0xE5 for CT_PHASE_DELAY measurement; otherwise, the
value must be 0xE4.
32 0x000000E4 R/W
0x425 CF_LCFG CF calibration pulse width configuration register. 32 0x00000000 R/W
0x471 TEMP_TRIM
Temperature sensor gain and offset, calculated during the
manufacturing process.
32 0x00000000 R
0x472 CHIP_ID_HI Chip identification, 32 MSBs. 32 0x00000000 R
0x473 CHIP_ID_LO Chip identification, 32 LSBs. 32 0x00000000 R
0x480 Run Write this register to 1 to start the measurements. 16 0x0000 R/W
0x481 CONFIG1 Configuration Register 1. 16 0x0300 R/W
0x485 ANGL_AV_AI
Time between positive to negative zero crossings on Phase A
voltage and current.
16 0x0000 R
0x488 ANGL_AI_BI
Time between positive to negative zero crossings on Phase A and
Phase B currents.
16 0x0000 R
0x48B DIP_CYC Voltage RMS_OC dip detection cycle configuration. 16 0xFFFF R/W
0x48C SWELL_CYC Voltage RMS_OC swell detection cycle configuration. 16 0xFFFF R/W
0x490 CFMODE CFx configuration register. 16 0x0000 R/W
0x491 COMPMODE Computation mode register. Set this register to 0x0005. 16 0x0000 R/W
0x492 ACCMODE Accumulation mode register. 16 0x0000 R/W
0x493 CONFIG3 Configuration Register 3 for configuration of power quality settings. 16 0x0000 R/W
0x494 CF1DEN CF1 denominator register. 16 0xFFFF R/W
0x495 CF2DEN CF2 denominator register. 16 0xFFFF R/W
0x498 ZXTOUT Zero-crossing timeout configuration register. 16 0xFFFF R/W
0x499 ZXTHRSH Voltage channel zero-crossing threshold register. 16 0x0009 R/W
0x49A ZX_CFG Zero-crossing detection configuration register. 16 0x0000 R/W
0x49D PHSIGN Power sign register. 16 0x0000 R
0x4A8 CRC_RSLT This register holds the CRC of the configuration registers. 16 0x0000 R
0x4A9 CRC_SPI
The register holds the 16-bit CRC of the data sent out on the MOSI/RX
pin during the last SPI register read.
16 0x0000 R
0x4AC LAST_DATA_16
This register holds the data read or written during the last 16-bit
transaction on the SPI port. When using UART, this register holds
the lower 16 bits of the last data read or write.
16 0x0000 R
0x4AE LAST_CMD
This register holds the address and the read/write operation
request (CMD_HDR) for the last transaction on the SPI port.
16 0x0000 R
0x4AF CONFIG2
Configuration Register 2. This register controls the high-pass filter
(HPF) corner and the user period selection.
16 0x0C00 R/W
Data Sheet ADE9153A
Rev. 0 | Page 35 of 50
Address Name Description
Length
(Bits) Reset Access
0x4B0 EP_CFG Energy and power accumulation configuration. 16 0x0000 R/W
0x4B1 PWR_TIME Power update time configuration. 16 0x00FF R/W
0x4B2 EGY_TIME Energy accumulation update time configuration. 16 0x00FF R/W
0x4B4 CRC_FORCE This register forces an update of the CRC of configuration registers. 16 0x0000 W
0x4B6 TEMP_CFG Temperature sensor configuration register. 16 0x0000 R/W
0x4B7 TEMP_RSLT Temperature measurement result. 16 0x0000 R
0x4B9 AI_PGAGAIN This register configures the PGA gain for Current Channel A. 16 0x0000 R/W
0x4BF WR_LOCK This register enables the configuration lock feature. 16 0x0000 R/W
0x4C0 MS_STATUS_IRQ
The Tier 2 status register for the autocalibration mSure system
related interrupts. Any bit set in this register causes the
corresponding bit in the status register to be set. This register is
cleared on a read and all bits are reset. If a new status bit arrives
on the same clock on which the read occurs, the new status bit
remains set; in this way, no status bit is missed.
16 0x0000 R
0x4C1 EVENT_STATUS
Tier 2 status register for power quality event related interrupts.
See the MS_STATUS_IRQ description.
16 0x0000 R
0x4C2 CHIP_STATUS
Tier 2 status register for chip error related interrupts. See the
MS_STATUS_IRQ description.
16 0x0000 R
0x4DC UART_BAUD_SWITCH
This register switches the UART Baud rate between 4800 Baud
and 115,200 Baud. Writing a value of 0x0052 sets the Baud rate to
115,200 Baud; any other value maintains a Baud rate of 4800.
16 0x0000 W
0x4FE Version Version of the ADE9153B IC. 16 0x0000 R
0x600 AI_WAV_1 SPI burst read accessible registers organized functionally. See AI_WAV. 32 0x00000000 R
0x601 AV_WAV_1
SPI burst read accessible registers organized functionally. See
AV_WAV.
32 0x00000000 R
0x602 BI_WAV_1 SPI burst read accessible registers organized functionally. See BI_WAV. 32 0x00000000 R
0x604 AIRMS_1 SPI burst read accessible registers organized functionally. See AIRMS. 32 0x00000000 R
0x605 BIRMS_1 SPI burst read accessible registers organized functionally. See BIRMS. 32 0x00000000 R
0x606 AVRMS_1 SPI burst read accessible registers organized functionally. See AVRMS. 32 0x00000000 R
0x608 AWATT_1 SPI burst read accessible registers organized functionally. See AWATT. 32 0x00000000 R
0x60A AFVAR_1 SPI burst read accessible registers organized functionally. See AFVAR. 32 0x00000000 R
0x60C AVA_1 SPI burst read accessible registers organized functionally. See AVA. 32 0x00000000 R
0x60E APF_1 SPI burst read accessible registers organized functionally. See APF. 32 0x00000000 R
0x610 AI_WAV_2 SPI burst read accessible registers organized by phase. See AI_WAV. 32 0x00000000 R
0x611 AV_WAV_2 SPI burst read accessible registers organized by phase. See AV_WAV. 32 0x00000000 R
0x612 AIRMS_2 SPI burst read accessible registers organized by phase. See AIRMS. 32 0x00000000 R
0x613 AVRMS_2 SPI burst read accessible registers organized by phase. See AVRMS. 32 0x00000000 R
0x614 AWATT_2 SPI burst read accessible registers organized by phase. See AWATT. 32 0x00000000 R
0x615 AVA_2 SPI burst read accessible registers organized by phase. See AVA. 32 0x00000000 R
0x616 AFVAR_2 SPI burst read accessible registers organized by phase. See AFVAR. 32 0x00000000 R
0x617 APF_2 SPI burst read accessible registers organized by phase. See APF. 32 0x00000000 R
0x618 BI_WAV_2 SPI burst read accessible registers organized by phase. See BI_WAV. 32 0x00000000 R
0x61A BIRMS_2 SPI burst read accessible registers organized by phase. See BIRMS. 32 0x00000000 R
ADE9153A Data Sheet
Rev. 0 | Page 36 of 50
REGISTER DETAILS
Table 9. Register Details
Addr. Name Bits Bit Name Settings Description Reset Access
0x020 CONFIG0 [31:10] Reserved Reserved. 0x0 R
9 Reserved Reserved.
8 DISRPLPF
Set this bit to disable the
low-pass filter in the
fundamental reactive power
datapath.
0x0 R/W
7 DISAPLPF
Set this bit to disable the
low-pass filter in the total
active power datapath.
0x0 R/W
6 Reserved Reserved. 0x0 R
5 VNOMA_EN
Set this bit to use the
nominal phase voltage rms,
VNOM, in the computation
of the Phase A total
apparent power, AVA.
0x0 R
4 RMS_OC_SRC
This bit selects the samples
used for the RMS_OC
calculation.
0x0 R
0
x_WAV waveforms after the
high-pass filter and phase
compensation.
1
ADC samples, before the
high-pass filter.
3 ZX_SRC_SEL
This bit selects whether data
going into the zero-crossing
detection circuit comes
before the high-pass filter
and phase compensation, or
afterwards.
0x0 R
0
After the high-pass filter and
phase compensation.
1
Before the high-pass filter
and phase compensation.
2 INTEN_BI
Set this bit to enable the
integrator on Current
Channel B.
0x0 R/W
1 RESERVED Reserved. 0x0 R/W
0 HPFDIS
Set this bit to disable high-
pass filters in all current and
voltage channels.
0x0 R
0x023 BI_PGAGAIN [31:0] BI_GAIN
PGA gain for Current
Channel B.
0x0 R/W
0Gain = 1.
1Gain = 2.
10 Gain = 4.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

ADE9153AACPZ

Mfr. #:
Buy ADE9153AACPZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 1 PH Mtr IC w/ Auto Calibration
Lifecycle:
New from this manufacturer.
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