Data Sheet ADE9153A
Rev. 0 | Page 39 of 50
Addr. Name Bits Bit Name Settings Description Reset Access
15 FVARNL
This bit is set when
fundamental reactive energy
enters or exits the no load
condition.
0x0 R/W1
14 VANL
This bit is set when total
apparent energy enters or
exits the no load condition.
0x0 R/W1
13 WATTNL
This bit is set when total
active energy enters or exits
the no load condition.
0x0 R/W1
12 TEMP_RDY
This bit is set when there is a
new temperature reading
ready from the temperature
sensor.
0x0 R/W1
11 RMS_OC_RDY
This bit is set when the
RMS_OC values update.
0x0 R/W1
10 PWRRDY
This bit is set when the
power values in the AWATT_
ACC, AVA_ACC, and AFVAR_
ACC registers update, after
PWR_TIME 4 kSPS samples.
0x0 R/W1
9 DREADY
This bit is set when new
waveform samples are ready.
0x0 R/W1
8 EGYRDY
This bit is set when the power
values in the AWATTHR_x,
AVAHR, and AFVARHR
registers update, after EGY_
TIME 4 kSPS samples or line
cycles, depending on the
EGY_TMR_MODE bit in the
EP_CFG register.
0x0 R/W1
7 CF2
This bit is set when a CF2
pulse is issued, when the
CF2 pin goes from a high to
low state.
0x0 R/W1
6 CF1
This bit is set when a CF1
pulse is issued, when the
CF1 pin goes from a high to
low state.
0x0 R/W1
5 REVPCF2
This bit is set to indicate if
the CF2 polarity changed
sign. For example, if the last
CF2 pulse was positive
active energy and the next
CF2 pulse is negative active
energy, the REVPCF2 bit is
set. This bit is updated when
a CF2 pulse is output, when
the CF2 pin goes from high
to low.
0x0 R/W1
4 REVPCF1
This bit is set to indicate if the
CF1 polarity changed sign.
See the REVPCF2 description.
0x0 R/W1
3 Reserved Reserved. 0x0 R
