ADE9153AACPZ Datasheet ADE9153AACPZ-RL, ADE9153AACPZ | P31-P33

Data Sheet ADE9153A

Rev. 0 | Page 31 of 50

COMMUNICATION VERIFICATION REGISTERS

The ADE9153A includes three register that allow SPI operation

verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16

(Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers

record the received CMD_HDR and the last read or transmitted

data.

CRC OF CONFIGURATION REGISTERS

The configuration register CRC feature in the ADE9153A monitors

certain user and private register values. The results are stored in

the CRC_RSLT register. When enabled, the ADE9153A generates

an interrupt on

IRQ

if any of the monitored registers change the

value of the CRC_RSLT register.

CONFIGURATION LOCK

The configuration lock feature prevents changes to the ADE9153A

configuration. To enable this feature, write 0x3C64 to the

WR_LOCK register. To disable the feature, write 0x4AD1.

To determine whether this feature is active, read the

WR_LOCK register, which reads as 1 if the protection is

enabled and 0 if it is disabled.

When this feature is enabled, it prevents writing to addresses

from Address 0x000 to Address 0x073 and Address 0x400 to

Address 0x4FE.

ADE9153A Data Sheet

Rev. 0 | Page 32 of 50

Table 8. Register Summary

Address Name Description

Length

(Bits)

Reset Access

0x000 AIGAIN Phase A current gain adjust. 32 0x00000000 R/W

0x001 APHASECAL Phase A phase correction factor. 32 0x00000000 R/W

0x002 AVGAIN Phase A voltage gain adjust. 32 0x00000000 R/W

0x003 AIRMS_OS Phase A current rms offset for filter-based AIRMS calculation. 32 0x00000000 R/W

0x004 AVRMS_OS Phase A voltage rms offset for filter-based AVRMS calculation. 32 0x00000000 R/W

0x005 APGAIN Phase A power gain adjust for AWATT, AVA, and AFVAR calculations. 32 0x00000000 R/W

0x006 AWATT_OS Phase A total active power offset correction for AWATT calculation. 32 0x00000000 R/W

0x007 AFVAR_OS

Phase A fundamental reactive power offset correction for AFVAR

calculation.

32 0x00000000 R/W

0x008 AVRMS_OC_OS Phase A voltage rms offset for fast rms, AVRMS_OC calculation. 32 0x00000000 R/W

0x009 AIRMS_OC_OS Phase A current rms offset for fast rms, AIRMS_OC calculation. 32 0x00000000 R/W

0x010 BIGAIN Phase B current gain adjust. 32 0x00000000 R/W

0x011 BPHASECAL Phase B correction factor. 32 0x00000000 R/W

0x013 BIRMS_OS Phase B current rms offset for filter-based BIRMS calculation. 32 0x00000000 R/W

0x019 BIRMS_OC_OS Phase B current rms offset for fast rms, BIRMS_OC calculation. 32 0x00000000 R/W

0x020 CONFIG0 DSP configuration register. 32 0x00000000 R/W

0x021 VNOM

Nominal phase voltage rms used in the calculation of apparent

power, AVA, when the VNOMA_EN bit is set in the CONFIG0 register.

32 0x00000000 R/W

0x022 DICOEFF

Value used in the digital integrator algorithm. If the integrator is

turned on, with INTEN_BI equal to 1 in the CONFIG0 register, it is

recommended to leave this register at the default value.

32 0x00000000 R/W

0x023 BI_PGAGAIN PGA gain for Current Channel B ADC. 32 0x00000000 R/W

0x030 MS_ACAL_CFG mSure autocalibration configuration register. 32 0x00000000 R/W

0x045 MS_AICC_USER

User input Current Channel A CC value for mSure initialization and

threshold calculation.

32 0x00000000 R/W

0x046 MS_BICC_USER

User input Current Channel B CC value for mSure initialization and

threshold calculation.

32 0x00000000 R/W

0x047 MS_AVCC_USER

User input Voltage Channel CC value for mSure initialization and

threshold calculation.

32 0x00000000 R/W

0x049 CT_PHASE_DELAY

Phase delay of the CT used on Current Channel B. This register is

in 5.27 format and expressed in degrees.

32 0x00000000 R/W

0x04A CT_CORNER

Corner frequency of the CT. This value is calculated from the

CT_PHASE_DELAY value.

32 0x00000000 R/W

0x04C VDIV_RSMALL

This register holds the resistance value, in Ω, of the small resistor

in the resistor divider.

32 0x00000000 R/W

0x200 AI_WAV

Instantaneous Current Channel A waveform processed by the DSP

at 4 kSPS.

32 0x00000000 R

0x201 AV_WAV

Instantaneous voltage channel waveform processed by the DSP

at 4 kSPS.

32 0x00000000 R

0x202 AIRMS Phase A filter-based current rms value updated at 4 kSPS. 32 0x00000000 R

0x203 AVRMS Phase A filter-based voltage rms value updated at 4 kSPS. 32 0x00000000 R

0x204 AWATT Phase A low-pass filtered total active power updated at 4 kSPS. 32 0x00000000 R

0x206 AVA Phase A total apparent power updated at 4 kSPS. 32 0x00000000 R

0x207 AFVAR Phase A fundamental reactive power updated at 4 kSPS. 32 0x00000000 R

0x208 APF Phase A power factor updated at 1.024 sec. 32 0x00000000 R

0x209 AIRMS_OC

Phase A current fast rms calculation; one cycle rms updated every

half cycle.

32 0x00000000 R

0x20A AVRMS_OC

Phase A voltage fast rms calculation; one cycle rms updated every

half cycle.

32 0x00000000 R

Data Sheet ADE9153A

Rev. 0 | Page 33 of 50

Address Name Description

Length

(Bits) Reset Access

0x210 BI_WAV

Instantaneous Phase B Current Channel waveform processed by

the DSP at 4 kSPS.

32 0x00000000 R

0x212 BIRMS Phase B filter-based current rms value updated at 4 kSPS. 32 0x00000000 R

0x219 BIRMS_OC

Phase B Current fast rms calculation; one cycle rms updated every

half cycle.

32 0x00000000 R

0x220 MS_ACAL_AICC Current Channel A mSure CC estimation from autocalibration. 32 0x00000000 R

0x221 MS_ACAL_AICERT Current Channel A mSure certainty of autocalibration. 32 0x00000000 R

0x222 MS_ACAL_BICC Current Channel B mSure CC estimation from autocalibration. 32 0x00000000 R

0x223 MS_ACAL_BICERT Current Channel B mSure certainty of autocalibration. 32 0x00000000 R

0x224 MS_ACAL_AVCC Voltage channel mSure CC estimation from autocalibration. 32 0x00000000 R

0x225 MS_ACAL_AVCERT Voltage channel mSure certainty of autocalibration. 32 0x00000000 R

0x240 MS_STATUS_CURRENT

The MS_STATUS_CURRENT register contains bits that reflect the

present state of the mSure system.

32 0x00000000 R

0x241 VERSION_DSP

This register indicates the version of the ADE9153B DSP after the

user writes run = 1 to start measurements.

32 0x00000000 R

0x242 VERSION_PRODUCT This register indicates the version of the product being used. 32 0x0009153A R

0x39D AWATT_ACC

Phase A accumulated total active power, updated after PWR_TIME

4 kSPS samples.

32 0x00000000 R

0x39E AWATTHR_LO

Phase A accumulated total active energy, least significant bits

(LSBs). Updated according to the settings in the EP_CFG and

EGY_TIME registers.

32 0x00000000 R

0x39F AWATTHR_HI

Phase A accumulated total active energy, most significant bits

(MSBs). Updated according to the settings in the EP_CFG and

EGY_TIME registers.

32 0x00000000 R

0x3B1 AVA_ACC

Phase A accumulated total apparent power, updated after

PWR_TIME 4 kSPS samples.

32 0x00000000 R

0x3B2 AVAHR_LO

Phase A accumulated total apparent energy, LSBs. Updated

according to the settings in the EP_CFG and EGY_TIME registers.

32 0x00000000 R

0x3B3 AVAHR_HI

Phase A accumulated total apparent energy, MSBs. Updated

according to the settings in the EP_CFG and EGY_TIME registers.

32 0x00000000 R

0x3BB AFVAR_ACC

Phase A accumulated fundamental reactive power. Updated after

PWR_TIME 4 kSPS samples.

32 0x00000000 R

0x3BC AFVARHR_LO

Phase A accumulated fundamental reactive energy, LSBs. Updated

according to the settings in the EP_CFG and EGY_TIME registers.

32 0x00000000 R

0x3BD AFVARHR_HI

Phase A accumulated fundamental reactive energy, MSBs. Updated

according to the settings in the EP_CFG and EGY_TIME registers.

32 0x00000000 R

0x3EB PWATT_ACC

Accumulated positive total active power from the AWATT register;

updated after PWR_TIME 4 kSPS samples.

32 0x00000000 R

0x3EF NWATT_ACC

Accumulated negative total active power from the AWATT

32 0x00000000 R

0x3F3 PFVAR_ACC

Accumulated positive fundamental reactive power from the

AFVAR register, updated after PWR_TIME 4 kSPS samples.

32 0x00000000 R

0x3F7 NFVAR_ACC

Accumulated negative fundamental reactive power from the

AFVAR register, updated after PWR_TIME 4 kSPS samples.

32 0x00000000 R

0x400 IPEAK Current peak register. 32 0x00000000 R

0x401 VPEAK Voltage peak register. 32 0x00000000 R

0x402 Status Tier 1 interrupt status register. 32 0x00000000 R/W

0x405 Mask Tier 1 interrupt enable register. 32 0x00000000 R/W

0x409 OI_LVL Overcurrent RMS_OC detection threshold level. 32 0x00FFFFFF R/W

0x40A OIA

Phase A overcurrent RMS_OC value. If overcurrent detection on this

channel is enabled with OIA_EN in the CONFIG3 register and

AIRMS_OC is greater than the OILVL threshold, this value is updated.

32 0x00000000 R

0x40B OIB Phase B overcurrent RMS_OC value. See the OIA description. 32 0x00000000 R

0x40E USER_PERIOD

User configured line period value used for RMS_OC when the

UPERIOD_SEL bit in the CONFIG2 register is set.

32 0x00500000 R/W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

ADE9153AACPZ

Mfr. #:

Buy ADE9153AACPZ

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized 1 PH Mtr IC w/ Auto Calibration

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ADE9153AACPZ

ADE9153AACPZ

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