ADE9153AACPZ Datasheet ADE9153AACPZ-RL, ADE9153AACPZ | P46-P48

ADE9153A Data Sheet

Rev. 0 | Page 46 of 50

Addr. Name Bits Bit Name Settings Description Reset Access

0x4AF CONFIG2 [15:13] Reserved Reserved. 0x0 R

12 UPERIOD_SEL

Set this bit to use a user

configured line period, in

USER_PERIOD, for RMS_OC

calculation. If this bit is clear,

the voltage line period is

used.

0x0 R/W

[11:9] HPF_CRN

High-pass filter corner (f

3 dB

)

enabled when the HPFDIS

bit in the CONFIG0 register

is equal to zero.

0x6 R/W

0 38.695 Hz.

1 19.6375 Hz.

10 9.895 Hz.

11 4.9675 Hz.

100 2.49 Hz.

101 1.2475 Hz.

110 0.625 Hz.

111 0.3125 Hz.

[8:0] Reserved Reserved. 0x0 R

0x4B0 EP_CFG [15:8] Reserved Reserved. 0x0 R

[7:5] NOLOAD_TMR

This register configures how

many 4 kSPS samples over

which to evaluate the no

load condition.

0x0 R/W

0 64 samples.

1 128 samples.

10 256 samples.

11 512 samples.

100 1024 samples.

101 2048 samples.

110 4096 samples.

111 Disable no load threshold.

4 Reserved Reserved. 0x0 R

3 RD_RST_EN

Set this bit to enable the

energy register read with

reset feature. If this bit is set,

when one of the AWATTHR_x,

AFVARHR, or AVAHR registers

are read, it is reset and begins

accumulating energy from

zero.

0x0 R/W

2 EGY_LD_ACCUM

If this bit is equal to zero, the

internal energy register is

added to the user accessible

energy register. If this bit is

set, the internal energy

accessible energy register

when the EGYRDY event

occurs.

0x0 R/W

Data Sheet ADE9153A

Rev. 0 | Page 47 of 50

Addr. Name Bits Bit Name Settings Description Reset Access

1 EGY_TMR_MODE

This bit determines whether

energy is accumulated based

on the number of 4 kSPS

samples or zero-crossing

events configured in the

EGY_TIME register.

0x0 R/W

Accumulate energy based on

4 kSPS samples.

Accumulate energy based

on the zero-crossing events.

0 EGY_PWR_EN

Set this bit to enable the

energy and power

accumulator when the run

bit is also set.

0x0 R/W

0x4B4 CRC_FORCE [15:1] Reserved Reserved. 0x0 R

0 FORCE_CRC_UPDATE

Write this bit to force the

configuration register CRC

calculation to start. When

the calculation is complete,

the CRC_DONE bit is set in

the status register.

0x0 W1

0x4B6 TEMP_CFG [15:4] Reserved Reserved. 0x0 R

3 TEMP_START

Set this bit to manually

request a new temperature

sensor reading. The new

temperature reading is

available in 1 ms, indicated by

the TEMP_RDY bit in the

status register. Note that this

bit is self clearing.

0x0 W1

2 TEMP_EN

Set this bit to enable the

temperature sensor.

0x0 R/W

[1:0] TEMP_TIME

These bits select the

number of temperature

readings to average.

0x0 R/W

1 sample. New temperature

measurement every 1ms.

256 samples. New

temperature measurement

every 256 ms.

512 samples. New

temperature measurement

every 512 ms.

1024 samples. New

temperature measurement

every 1 sec.

0x4B7 TEMP_RSLT [15:12] Reserved Reserved. 0x0 R

[11:0] TEMP_RESULT

12-bit temperature sensor

result

0x0 R

0x4B9 AI_PGAGAIN [15:5] Reserved Reserved. 0x0 R

4 AI_SWAP

This bit sets the signal side

of the PGA, meaning that

the IAP and IAN pins can be

swapped by setting this bit.

This bit must be set to 1 for

proper operation, only set

to 0 if sensor is connected in

reverse.

0x0 R/W

0Signal on IAN.

1Signal on IAP.

ADE9153A Data Sheet

Rev. 0 | Page 48 of 50

Addr. Name Bits Bit Name Settings Description Reset Access

3 Reserved Reserved. 0x0 R

[2:0] AI_GAIN

PGA gain for Current

Channel A.

0x0 R/W

10 Gain = 16.

11 Gain = 24.

100 Gain = 32.

101 Gain = 38.4.

0x4C0 MS_STATUS_IRQ 15 Reserved Reserved. 0x0 R

14 MS_SYSRDY

This bit is set when a new

run of mSure is ready to be

enabled after a run of mSure

is disabled. A new run is

ready less than 1 sec after

disabling the previous run.

0x0 R

13 MS_CONFERR

This bit is set if there is an

invalid configuration of

mSure autocalibration. Fix

the configuration error and

try it running again.

0x0 R

12 MS_ABSENT

When this bit is set, mSure is

not detected on the channel

that was last enabled.

0x0 R

11 Reserved Reserved. 0x0 R

10 Reserved Reserved. 0x0 R

9 Reserved Reserved. 0x0 R

8 Reserved Reserved. 0x0 R

7 Reserved Reserved. 0x0 R

6 Reserved Reserved. 0x0 R

5 Reserved Reserved. 0x0 R

4 Reserved Reserved. 0x0 R

3 MS_TIMEOUT

This bit is set when mSure

times out after 600 sec.

0x0 R

2 Reserved Reserved. 0x0 R

1 MS_READY

This bit is set when the

mSure result registers first

start to be populated (after

the 8 sec block). Then, this

bit is set every second for

when the value is updated

until mSure is stopped.

0x0 R

0 MS_SHIFT

This bit is set when there is a

shift in the mSure CC value

in the middle of a run,

meaning that the value

found for the xCC shifted

and another run of mSure

with the same settings must

be performed to verify the

shift.

0x0 R

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

ADE9153AACPZ

Mfr. #:

Buy ADE9153AACPZ

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized 1 PH Mtr IC w/ Auto Calibration

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New from this manufacturer.

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ADE9153AACPZ

ADE9153AACPZ

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