NXP Semiconductors
NHS3152
Therapy adherence resistive monitor
NHS3152 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 3.03 — 15 June 2018
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Ball Symbol Type Description
PIO0_10 I/O GPIO
CT32B_M0 O 32-bit timer match output 0
B5
SWCLK I ARM SWD clock
PIO0_11 I/O GPIO
CT32B_M1 O 32-bit timer match output 1
C5
SWDIO I/O ARM SWD I/O
Analog I/O
[4]
E1 AN0_0 A to AN0_BUS0
E2 AN0_1 A to AN0_BUS1
D3 AN0_2 A to AN0_BUS2
E3 AN0_3 A to AN0_BUS3
D4 AN0_4 A to AN0_BUS4
D5 AN0_5 A to AN0_BUS5
Radio
E4 LA A NFC antenna/coil terminal A
E5 LB A NFC antenna/coil terminal B
Reset
A3 RESETN I external reset input
[5]
[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins
depend on the function selected through the IOCONFIG register block.
[2] If external wake-up is enabled on this pin, it must be pulled HIGH before entering Deep power-down mode and pulled
LOW for a minimum of 100 μs to exit Deep power-down mode.
[3] Open drain, no pull-up or pull down.
[4] The analog port is a 6-input analog I/O port with enable control for each pad.
[5] A LOW on this pin resets the device. This reset causes I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0. It has weak pull-up to V
DDBAT
or internal NFC voltage (whichever is highest).
8 Functional description
8.1 ARM Cortex-M0+ core
Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed
description of the ARM Cortex-M0+ processor.
The NHS3152 ARM Cortex-M0+ core has the following configuration:
• System options
– Nested Vectored Interrupt Controller (NVIC)
– Fast (single-cycle) multiplier
– System tick timer
– Support for wake-up interrupt controller
– Vector table remapping register
– Reset of all registers
• Debug options
