NHS3152UK/A1Z Datasheet NHS3152DBUL, NHS3152UK/A1Z, NHS3152THADADKUL | P22-P24

NXP Semiconductors

NHS3152

Therapy adherence resistive monitor

Product data sheet Rev. 3.03 — 15 June 2018

22 / 51

8.8 Fast general-purpose parallel I/O

The GPIO registers control device pins that are not connected to a specific peripheral

function. Pins may be dynamically configured as inputs or outputs. Multiple outputs can

be set or cleared in one write operation.

The NHS3152 uses accelerated GPIO functions:

• GPIO registers are on the ARM Cortex-M0+ I/O bus for fastest possible single-cycle I/O

timing

• An entire port value can be written in one instruction

• Mask, set, and clear operations are supported for the entire port

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot

be moved to another pin.

NXP Semiconductors

NHS3152

Therapy adherence resistive monitor

Product data sheet Rev. 3.03 — 15 June 2018

23 / 51

8.8.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation

• Direction control of individual bits

• After reset, all I/Os default to GPIO inputs without pull-up or pull-down resistors; The

C-bus true open-drain pins PIO0_4 and PIO0_5 and the SWD pins PIO0_10 and

PIO0_11 are exceptions

• Pull-up/pull-down Configuration, Repeater, and Open-drain modes can be programmed

through the IOCON block for each GPIO pin

• Direction (input/output) can be set and cleared individually per pin

• Pin direction bits can be toggled

8.9 I

C-bus controller

8.9.1 Features

Standard I

C-bus compliant interfaces may be configured as master, slave, or master/

slave.

• Arbitration is handled between simultaneously transmitting masters without corruption

of serial data on the bus

• Programmable clock allows adjustment of I

C-bus transfer rates

• Data transfer is bidirectional between masters and slaves

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization is used as a handshake mechanism to suspend and

resume serial transfer

• Supports Standard-mode (100 kbit/s) and Fast-mode (400 kbit/s)

• Optional recognition of up to four slave addresses

• Monitor mode allows observing all I

C-bus traffic, regardless of slave address

• The I

C-bus can be used for test and diagnostic purposes

• The I

C-bus contains a standard I

C-bus compliant interface with two pins

• Possibility to wake up NHS3152 on matching I

C-bus slave address

NXP Semiconductors

NHS3152

Therapy adherence resistive monitor

Product data sheet Rev. 3.03 — 15 June 2018

24 / 51

8.9.2 General description

Two types of data transfers are possible on the I

C-bus, depending on the state of the

direction bit (R/W):

• Data transfer from a master transmitter to a slave receiver

The first byte transmitted by the master is the slave address. Next follows a number of

data bytes. The slave returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver

The master transmits the first byte (the slave address). The slave then returns an

acknowledge bit. The slave then transmits the data bytes to the master. The master

returns an acknowledge bit after all received bytes other than the last byte. At the end

of the last received byte, a not-acknowledge is returned. The master device generates

all of the serial clock pulses and the START and STOP conditions. A transfer is ended

with a STOP condition or with a repeated START condition. As a repeated START

condition is also the beginning of the next serial transfer, the I

C-bus is not released.

The I

C-bus interface is byte oriented and has four operating modes: Master transmitter

mode, Master receiver mode, Slave transmitter mode, and Slave receiver mode.

The I

C-bus interface is completely I

C-bus compliant, supporting the ability to power off

the NHS3152 independent of other devices on the same I

C-bus.

The I

C-bus interface requires a minimum 2 MHz system clock to operate in Normal

mode, and 8 MHz for Fast-mode.

8.9.3 I

C-bus pin description

Table 11. I

C-bus pin description

Pin Type Description

SDA I/O I

C-bus serial data

SCL I/O I

C-bus serial clock

The I

C-bus pins must be configured through the PIO0_4 and PIO0_5 registers for

Standard-mode or Fast-mode. The I

C-bus pins are open-drain outputs and fully

compatible with the I

C-bus specification.

8.10 SPI controller

8.10.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments Synchronous Serial Interface

(SSI), and National Semiconductor Microwire buses

• Synchronous Serial Communication

• Supports master or slave operation

• Eight-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51

NHS3152UK/A1Z

Mfr. #:

Buy NHS3152UK/A1Z

Manufacturer:

NXP Semiconductors

Description:

Board Mount Temperature Sensors NTAG NHS3152 NFC Therapy Adherence

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

NHS3152UK/A1Z

NHS3152UK/A1Z

Products related to this Datasheet