NXP Semiconductors
NHS3152
Therapy adherence resistive monitor
NHS3152 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 3.03 — 15 June 2018
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t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
70 %
30 %
70 %
30 %
t
HD;DAT
SCL
1 / f
SCL
70 %
30 %
70 %
30 %
t
VD;DAT
t
HIGH
t
LOW
t
SU;DAT
Figure 16. I
2
C-bus pins clock timing
11.3 SPI interfaces
Table 30. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master
full-duplex mode
[1]
50 - - nst
cy(clk)
clock cycle time
when only transmitting
[1]
40 - - ns
2.4 V ≤ V
DD
< 3.6 V
[2]
15 - - ns
2.0 V ≤ V
DD
< 2.4 V
[2]
20 - - ns
t
SU;DAT
data setup time
1.8 V ≤ V
DD
< 2.0 V
[2]
24 - - ns
t
HD;DAT
data hold time
[2]
0 - - ns
t
v(Q)
data output valid time
[2]
- - 10 ns
t
h(Q)
data output hold time
[2]
0 - - ns
SPI slave
T
cy(PCLK)
PCLK cycle time
[3]
[4]
0 - - ns
t
HD;DAT
data hold time
[3]
[4]
3 × T
cy(PCLK)
+ 4 - - ns
t
v(Q)
data output valid time
[3]
[4]
- - 3 × T
cy(PCLK)
+ 11 ns
t
h(Q)
data output hold time
[3]
[4]
- - 2 × T
cy(PCLK)
+ 5 ns
[1] t
cy(clk)
= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate t
cy(clk)
is a function of:
• The main clock frequency f
main
• The SPI peripheral clock divider (SSPCLKDIV)
• The SPI SCR parameter (specified in the SSP0CR0 register)
• The SPI CPSDVSR parameter (specified in the SPI clock prescale register)
[2] T
amb
= −40 °C to +105 °C
[3] t
cy(clk)
= 12 × T
cy(PCLK)
[4] T
amb
= 25 °C for normal voltage supply: V
DD
= 3.3 V
