LTC3676/LTC3676-1
15
3676fe
For more information www.linear.com/LTC3676
OPERATION
INTRODUCTION
The LTC3676 is a complete power management solution
for portable microprocessors and peripheral devices. It
generates a total of eight voltage rails for supplying power
to the processor core, DDR memory, I/O, always-on real-
time clock and HDD functions. Supplying the voltage rails
are an always-on low quiescent current 25mA LDO, two
2.5A step-down regulators, two 1.5A step-down regula
-
tors, and
three 300mA low dropout regulators. Supporting
the
multiple regulators is a highly configurable power-on
sequencing capability, dynamic voltage scaling DAC output
voltage control, a pushbutton interface controller, control
via an I
2
C interface, and extensive status and interrupt
outputs.
The LTC3676-1 supports DDR memory applications by
replacing the LTC3676 LDO4 feedback and enable pins
with VDDQIN and VTTR pins. The DDR V
DD
supply is
connected to the LTC3676-1 VDDQIN pin. A buffered DDR
termination voltage equal to one half the voltage on VD
-
DQIN is output on VTTR. The VTTR voltage is connected
internally on the LTC3676-1 to the reference side of the
Buck1 error amplifier. When Buck1 is configured with a
gain of one, its output can be used as at DDR termination
supply. Table1 shows the
functional differences between
the LTC3676 and LTC3676-1.
Table 1. Functional Differences LTC3676 vs LTC3676-1
LTC3676 LTC3676-1
Buck1 Default
Frequency
2.25MHz 1.125MHz
Buck1 Default
Mode
Pulse-Skipping Forced Continuous
Buck1 Output External Resistor Divider.
Slewing DAC Reference
External Unity Gain.
VTTR Reference
LDO4 Enable
EN_L4 Pin or I
2
C I
2
C
LDO4 Output External Resistor Divider.
725mV Reference
I
2
C Select 1 of 4 Fixed
Outputs
FB_L4 Pin External Resistor Divider —
EN_L4 Pin Enable LDO4. —
VDDQIN Pin — Connect to DDR Memory
Supply
VTTR Pin — Buffered Output Equals
One-Half VDDQIN
I
2
C Device
Address
Write = 0x78
Read = 0x79
Write = 0x7A
Read = 0x7B
Always-On 25mA Low Dropout Regulator
The LTC3676 includes a low quiescent current low dropout
regulator that remains powered whenever a valid supply is
present on V
IN
. The always-on LDO1 remains active until
V
IN
drops below 2.0V (typical). This is below the 2.5V
undervoltage threshold in effect for the rest of the LTC3676
circuits. The always-on LDO is used to provide power to a
standby microcontroller, real-time clock, or other keep-alive
circuits. The LDO is guaranteed to support a 25mA load. A
1µF low impedance ceramic bypass capacitor from LDO1 to
GND is required for compensation. A power good monitor
pulls RSTO low whenever
LDO1 is 8%
below its regulation
target. LDO1 has current limit circuitry to protect from
short circuit and overloading. The output voltage of LDO1
is set with a resistor divider connected from LDO1 output
pin to the feedback pin FB_L1, as shown in Figure 2. The
output voltage is calculated using the following formula:
V
LDO1
= 725 • 1+
R2
⎛
⎝
⎜
⎞
⎠
⎟
mV
( )
300mA Low Dropout Regulators
Three LDO regulators on the LTC3676 will each deliver
up to 300mA output. Each LDO regulator has separate
input supply to help manage power loss in the LDO output
devices. The LDO regulators are enabled by pin input or I
2
C
command register. When disabled, the regulator outputs
are pulled to ground through a 625Ω resistor. A low ESR
1µF ceramic capacitor should be tied from the LDO output
to ground. The 300mA LDO regulators have current limit
control circuits. The LDO input voltages, V
IN_L2
, V
IN_L3
,
and V
IN_L4
must be at potential of V
IN
or less.
The LDO regulator I
2
C command register controls are
shown in Table 2 and Table 3.
ERROR
AMP
BUCK1
PVINB1
SW1
FB_B1
C
FB
R1 C
OUT
3676 F01
DDR
REF
VDDQIN/2
VDDQIN/2
VDDQIN
VTTR
PWM
Figure 1. V
TT
Buck Regulator and VTTR Reference Block Diagram
