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LTC3676IUJ-1#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
LTC3676/LTC3676-1
19
3676fe
For more information www.linear.com/LTC3676
OPERATION
Table 6. Buck3 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK3[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK3[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK3[2] 0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK3[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK3[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK3[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK3[7] 0*
1
Buck3 Disabled if EN_B3 Pin Is Low
Buck3 Enabled
*denotes default power-on value.
Table 7. Buck4 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK4[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK4[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK4[2] 0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK4[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK4[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK4[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK4[7] 0*
1
Buck4 Disabled if EN_B4 Pin Is Low
Buck4 Enabled
*denotes default power-on value.
SLEWING DAC REFERENCE OPERATION
Each LTC3676 step-down switching regulators error am-
plifier reference
voltage is supplied by a 5-bit DAC with
an output voltage range of 412.5mV to 800mV in 12.5mV
steps. One of two 5-bit codes stored in I
2
C command
registers is selected for input to the DAC. When a change
in code is detected by the DAC control circuits, the output
of the DAC is slewed at 3.5mV/µs to the new value.
Dynamic Voltage Scaling
Table 8 shows the command registers used to control
dynamic voltage scaling (DVS) of the step-down switching
regulators input reference DAC. The command register
bits DVB1A[4:0] and DVB1B[4:0] store two 5-bit inputs
to the DAC reference for Buck1. The bit stored in com
-
mand register
DVB1A[5] selects either the 5 bits stored
in DVB1A[4:0] or DVB1B[4:0] DAC as input to the DAC
reference. Buck2, Buck3, and Buck4 operate the same
way using their assigned “A” and “B” command registers
shown in Table 8. When the DAC detects a change in its
input code it automatically slews to the new value at a rate
of 3.5mV/µs. A DVS can be initiated using the I
2
C select
bit or using the VSTB pin.
The LTC3676 VSTB pin HIGH selects the 5 bits stored in
all four DVBx “
B” registers. This facilitates a simultaneous
DAC slew between the values in the “A” registers and the
values in the “B” registers. The VSTB pin is logically ORed
with the I
2
C command register bit. If the I
2
C select bit is
already set high, the “B” registers are already selected and
VSTB will have no effect. If no change in output is desired
using the VSTB pin, set the value in the “A” register equal
to the value in the “B”.
Command register bits DVB1B[5], DVB2B[5], DVB3B[5],
and DVB4B[5] control whether the PGOOD status pin is
pulled low while the DAC output is slewing. The default
command register setting is to pull PGOOD pin low dur
-
ing DAC slew. During the DVS, PGOOD will be held low
for just the duration of the DVS and the PGSTAT register
is not affected.
Figure 5. Dynamic Voltage Scaling
V
OUT
200mV/DIV
PGOOD
5V/DIV
VSTB
5V/DIV
100µs/DIV
3676 F05
LTC3676/LTC3676-1
20
3676fe
For more information www.linear.com/LTC3676
OPERATION
Table 8. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control
Command Registers
COMMAND
REGISTER[BIT] VALUE SETTING
DVB1A[4:0] bbbbb Buck1 Reference DAC Input A
DVB1A[5] 0*
1
Select DVB1A[4:0]
Select DVB1B[4:0]
DVB1B[4:0]
bbbbb Buck1 Reference DAC Input B
DVB1B[5] 0*
1
Pull PGOOD Low Slewing Buck1
Do Not Pull PGOOD Slewing Buck1
DVB2A[4:0]
bbbbb Buck2 Reference DAC Input A
DVB2A[5] 0*
1
Select DVB2A[4:0]
Select DVB2B[4:0]
DVB2B[4:0]
bbbbb Buck2 Reference DAC Input B
DVB2B[5] 0*
1
Pull PGOOD Low Slewing Buck2
Do Not Pull PGOOD Slewing Buck2
DVB3A[4:0]
bbbbb Buck3 Reference DAC Input A
DVB3A[5] 0*
1
Select DVB3A[4:0]
Select DVB3B[4:0]
DVB3B[4:0]
bbbbb Buck3 Reference DAC Input B
DVB3B[5] 0*
1
Pull PGOOD Low Slewing Buck3
Do Not Pull PGOOD Slewing Buck3
DVB4A[4:0]
bbbbb Buck4 Reference DAC Input A
DVB4A[5] 0*
1
Select DVB4A[4:0]
Select DVB4B[4:0]
DVB4B[4:0]
bbbbb Buck4 Reference DAC Input B
DVB4B[5] 0*
1
Pull PGOOD Low Slewing Buck4
Do Not Pull PGOOD Slewing Buck4
*denotes default power-on value.
PUSHBUTTON OPERATION
Operating Mode State Diagram
Figure 6 shows the state diagram of the LTC3676 enable
and sequence controller. First application of power to
V
IN
pin brings the controller to the power-on reset/hard
reset (POR/HRST) state. In this state the I
2
C command
registers have been set to their default values, only LDO1
is operating, and the device is waiting for pushbutton or
PWR_ON inputs. Regulator enable pins and command
register enable bits are ignored in POR/HRST state. In the
POR/HRST state V
IN
draws typically 12µA.
Power Up Using Pushbutton
When the ON pin is held low for 400ms the WAKE pin is
pulled high, enable pins are recognized, and the five second
PWR_ON timer is started. If in the ON state and PWR_ON
is low or a fault is detected, then WAKE is brought low and
after a 1 second power-down time, the STANDBY state
is entered. In STANDBY, the enable bits in the command
registers are cleared and enable pins are ignored. Table9
shows the control of command registers, enables, and
WAKE at each state.
The 5 second power-on state is intended for the system to
detect that power rails are correct and either drive PWR_ON
pin high or set command register bit CNTRL[7] high to
keep the rails active. If there were a
system level problem
Figure 6. LTC3676 Operating Mode State Diagram
ENABLE
ALLOWED AND
WAKE HIGH
ENABLE
INHIBITED AND
WAKE LOW
POR/HRST
V
IN
HIGH
ON 400ms
OR PWR_ON
ON 10 SEC
OR I
2
C HRST
ON 400ms
OR PWR_ON
PWR_ON
OR FAULT
ON 10 SEC
OR I
2
C HRST
ON 10 SEC
OR I
2
C HRST
1 SEC OFF
TIMER
HRST
3676 F06
1 SEC OFF
TIMER
STANDBY
5 SEC
PWR_ON
TIMER
ON
STANDBY
LTC3676/LTC3676-1
21
3676fe
For more information www.linear.com/LTC3676
OPERATION
keeping the processor from driving PWR_ON, then the
LTC3676 will pull WAKE low, shut off all regulators, and
enter the STANDBY state. The STANDBY state is also a
low power, 12µA (typical) state.
Table 9. Register, Enable, WAKE Control During Operating
Mode State Control
STATE REGISTERS ENABLES WAKE
POR/HRST DEFAULT R/W Inhibited LOW
5 SEC PWR_ON TIMER R/W Allowed HIGH
ON R/W Allowed HIGH
1 SEC OFF TIMER HRST Set to POR
Defaults
Sequence Down LOW
1 SEC OFF TIMER
STANDBY
I
2
C Enable
and SW
Mode Bits
Cleared
Sequence Down LOW
STANDBY R/W Inhibited LOW
Power Down Using Pushbutton
When in the ON state, the system controller is responsible
for deciding what action to take when a pushbutton event
occurs. By monitoring the IRQ status pin and IRQSTAT[0]
status register bit, the controller can detect a pushbutton
request. If a power-down into standby state is desired
then the controller should drive PWR_ON low and set
command register bit CNTRL[7] low.
Button Status Indication
When a pushbutton pulls ON low for 50ms in the ON state,
IRQ is pulled low and the PB status bit in the IRQSTAT[0]
status register is set. IRQ and the IRQSTAT status bit are
active while ON is low or for a minimum of 50ms.
Power Up and Down with PWR_ON
The PWR_ON pin is an alternative way to power up the
LTC3676 instead of using the ON pin. When PWR_ON is
driven high or
command register
CNTRL[7] is set high,
WAKE is pulled HIGH and the LTC3676 passes through
the 5 second PWR_ON timer to the ON state. Figure 9
shows PWR_ON and WAKE timing. WAKE stays high for
a minimum of 5 seconds.
Figure 8. Power-Down Using Pushbutton
50ms
IRQSTAT[0]
WAKE
<10 SEC
ON (PB)
IRQ
PWR_ON
(PIN OR I
2
C)
3676 F08
µC/µP CONTROL
3ms
Figure 7. Power Up Using Pushbutton
400ms
ON (PB)
WAKE
PWR_ON
(PIN OR I
2
C)
<5 SEC
3676 F07
µC/µP CONTROL
Figure 9. Power Up and Down with PWR_ON
PWR_ON
(PIN OR I
2
C)
WAKE
3676 F09
µC/µP CONTROL
5 SEC
3ms
3ms
POWER ON SEQUENCING
Enable Pin Operation
The LTC3676 enable pins facilitate pin-strapping output
rails to enable pins to up-sequence the LTC3676 regulators
in any order. Figure 10 shows an example of pin-strapped
sequence connections. The enable pins normally have a
0.8V (typical) input voltage threshold.
If any enable is driven high, the remaining enable input
thresholds switches to an accurate 400mV threshold. To
ensure separation of the sequenced rails, there is a built-
in 450µs delay from the enable pin threshold crossing to
the internal enable of the regulator. Figure 11 shows the
start-up timing of the example shown in Figure 10.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

LTC3676IUJ-1#TRPBF

Mfr. #:
Buy LTC3676IUJ-1#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Pwr M Solution for Application Processor
Lifecycle:
New from this manufacturer.
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