OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC3676IUJ-1#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
LTC3676/LTC3676-1
22
3676fe
For more information www.linear.com/LTC3676
Figure 11. Pin-Strapped Power-On Sequence
OPERATION
Software Control Mode
Once a power-up sequence is completed, each regulator
may be enabled and disabled individually by the system
as needed for power management requirements by using
the command register bit CNTRL[5]. When CNTRL[5] is
set high the regulators ignore the state of their enable pins
and respond only to I
2
C command register bit settings.
The software control mode bit is reset in the one second
standby and hard reset timer states so a pin strapped
sequence begins at the next LTC3676 power on.
Keep Alive Operation
Each regulator has a dedicated command register keep
alive bit that, when set, forces a regulator to be enabled
regardless of the enable pins, command register enable
WAKE
V
B1
V
B2
V
B3
V
B4
V
L2
V
L3
V
L4
0.4V
0.4V
450µs
1.2V
1.8V
2.5V
1.2V
1.2V
1.8V
2.8V
3676 F11
450µs
450µs
bits, or the operating state of the LTC3676. A hard reset
or fault shutdown resets the keep alive bits.
POWER OFF SEQUENCING
Sequence down command registers SQD1 and SQD2
are used to set the time, relative to WAKE falling, that a
regulator is disabled either by lowering PWR_ON, or a
fault induced shutdown. Table 10 shows register settings
for SQD1 and SQD2.
Table 10.Sequence Down Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
SQD1[1:0] 00*
01
10
11
Disable Buck1 at Falling W
AKE
Disable Buck1 at Falling WAKE + 100ms
Disable Buck1 at Falling WAKE + 200ms
Disable Buck1 at Falling WAKE + 300ms
SQD1[3:2] 00*
01
10
11
Disable Buck2 at Falling W
AKE
Disable Buck2 at Falling WAKE + 100ms
Disable Buck2 at Falling WAKE + 200ms
Disable Buck2 at Falling WAKE + 300ms
SQD1[5:4] 00*
01
10
11
Disable Buck3 at Falling W
AKE
Disable Buck3 at Falling WAKE + 100ms
Disable Buck3 at Falling WAKE + 200ms
Disable Buck3 at Falling WAKE + 300ms
SQD1[7:6] 00*
01
10
11
Disable Buck4 at Falling W
AKE
Disable Buck4 at Falling WAKE + 100ms
Disable Buck4 at Falling WAKE + 200ms
Disable Buck4 at Falling WAKE + 300ms
SQD2[1:0] 00*
01
10
11
Disable LDO2 at Falling W
AKE
Disable LDO2 at Falling WAKE + 100ms
Disable LDO2 at Falling WAKE + 200ms
Disable LDO2 at Falling WAKE + 300ms
SQD2[3:2] 00*
01
10
11
Disable LDO3 at Falling W
AKE
Disable LDO3 at Falling WAKE + 100ms
Disable LDO3 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
SQD2[5:4] 00*
01
10
11
Disable LDO4 at Falling W
AKE
Disable LDO4 at Falling WAKE + 100ms
Disable LDO4 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
*denotes default power-on value.
Figure 12 shows an example of a shutdown sequence. In
this example, the bits in command registers SQD1 and
SQD2 are set so that LDO2, LDO3, and LDO4 shut off at
the same time as WAKE. Buck2 and Buck4 shut off 100ms
after WAKE. Buck3 shuts off 200ms after wake and Buck1
shuts off 300ms after WAKE.
Figure 10. Pin-Strapped Power-On Sequence Application
LTC3676
V
IN
PWR_ON
3676 F10
V
B1
= 1.2V
V
B2
= 1.8V
V
B3
= 2.5V
V
B4
= 1.2V
V
L2
= 1.2V
V
L3
= 1.8V
V
L4
= 2.8V
WAKE
SW1
SW2
SW3
SW4
LDO2
LDO3
LDO4
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
EN_L4
ON
PWR_ON
LTC3676/LTC3676-1
23
3676fe
For more information www.linear.com/LTC3676
OPERATION
Figure 13. Output Low Voltage PGOOD and IRQ Timing
Figure 12. Power-Down Sequence
300ms
1.2V
WAKE
V
B1
V
B2
V
B3
V
B4
V
L2
V
L3
V
L4
1.8V
2.5V
1.2V
1.2V
1.8V
2.8V
3676 F12
200ms
100ms
FAULT DETECTION AND REPORTING
The LTC3676 has fault detection circuits that monitor
for V
IN
undervoltage, die overtemperature, and regulator
output undervoltage. Status of the fault detect circuits is
indicated by the IRQ and PGOOD pins and the IRQSTAT
and PGSTAT status registers.
V
IN
Undervoltage
The undervoltage (UV) circuit monitors the input supply
voltage, V
IN
, and when the voltage falls below 2.45V cre-
ates a FAULT condition that forces the LTC3676 into the
standby
state. The LTC3676 also provides a (UV) warning
that is triggered at user programmable V
IN
voltages as
shown in Table 11.
Table 11. Undervoltage Warning Threshold Command Register
Settings
COMMAND
REGISTER[BIT] VALUE FALLING V
IN
THRESHOLD
CNTRL[4:2] 000*
001
010
011
100
101
110
111
2.7V
2.8V
2.9V
3.0V
3.1V
3.2V
3.3V
3.4V
*
denotes default power-on value.
450µs
ENx
V
OUTx
PGOOD
IRQ
50µs
50µs
1ms
1ms
20ms
3676 F13
Over Temperature
To prevent thermal damage the LTC3676 incorporates an
overtemperature (OT) circuit. When the die temperature
reaches 155°C the OT circuits create a FAULT condition
that forces the LTC3676 into standby. When the OT cir
-
cuit detects
the temperature falls below 140°C the FAULT
condition
is cleared. The LTC3676 also has an OT warning
circuit that indicates the die temperature is approaching
the OT fault threshold. The OT warning threshold is user
programmable as shown in Table 12.
Table 12. Overtemperature Warning Threshold Command
Register Settings
COMMAND
REGISTER[BIT] VALUE OT WARNING THRESHOLD
CNTRL[1:0] 00*
01
10
11
10°C Below OT Fault
20°C Below OT Fault
30°C Below OT Fault
40°C Below OT Fault
*denotes default power-on value.
PGOOD Status Pin
The PGOOD open-drain status pin is pulled low when all
regulators are disabled. PGOOD is released when all enabled
regulator outputs are above 93% of programmed value.
When any enabled regulator output falls below 92% of its
programmed value for longer than 50µs the PGOOD pin is
pulled low. The 50µs transient filter on PGOOD prevents
PGOOD glitches due to transients. If the error condition
persists for longer than 20ms, the IRQ pin is pulled low and
status register IRQSTAT bit 2 is set to indicate a persistent
PGOOD fault. The PGOOD pin is held low for the duration
of the low output condition plus 1ms. Figure 13 shows the
timing of PGOOD during enable and fault events.
LTC3676/LTC3676-1
24
3676fe
For more information www.linear.com/LTC3676
OPERATION
PGSTAT and MSKPG Registers
The power good status of each regulator is accessible
through the LTC3676 I
2
C interface by reading the contents
of the PGSTAT status register. Table 13 shows the PGSTAT
register contents. The data in the PGSTATL register is held
for the length of the low voltage condition plus 1ms. The
data in the PGSTATRT register is held only for the duration
of the low voltage condition.
Table 13. Power Good Status Register
STATUS
REGISTER[BIT] VALUE REGULATOR OUTPUT LOW STATUS
PGSTAT[0] 0
1
Buck1 Output Low
Buck1 Output OK
PGSTA
T[1] 0
1
Buck2 Output Low
Buck2 Output OK
PGSTA
T[2] 0
1
Buck3 Output Low
Buck3 Output OK
PGSTA
T[3] 0
1
Buck4 Output Low
Buck4 Output OK
PGSTA
T[4] 0
1
LDO1 Output Low
LDO1 Output OK
PGSTA
T[5] 0
1
LDO2 Output Low
LDO2 Output OK
PGSTA
T[6] 0
1
LDO3 Output Low
LDO3 Output OK
PGSTA
T[7] 0
1
LDO4 Output Low
LDO4 Output OK
Each regulator has a corresponding bit in the MSKPG status
register as shown in Table 14. When set, a bit blocks the
PGOOD pin from being pulled low in the event of a low
output voltage fault from its matching regulator. Setting
a bit in the MSKPG command register does not mask the
status in the PGSTAT status register.
Table 14. Power Good Status Masking Command Register
COMMAND
REGISTER[BIT] VALUE
MSKPG [0] 0
1*
Mask Buck1 PGOOD Status
Pass Buck1 PGOOD Status
MSKPG [1] 0
1*
Mask Buck2 PGOOD Status
Pass Buck2 PGOOD Status
MSKPG [2] 0
1*
Mask Buck3 PGOOD Status
Pass Buck3 PGOOD Status
MSKPG [3] 0
1*
Mask Buck4 PGOOD Status
Pass Buck4 PGOOD Status
MSKPG [5] 0
1*
Mask LDO2 PGOOD Status
Pass LDO2 PGOOD Status
MSKPG [6] 0
1*
Mask LDO3 PGOOD Status
Pass LDO3 PGOOD Status
MSKPG [7] 0
1*
Mask LDO4 PGOOD Status
Pass LDO4 PGOOD Status
*denotes default power-on value.
IRQ Status Pin
The IRQ pin is pulled and latched low when undervoltage,
overtemperature or persistent PGOOD events occur. The
IRQ pin is cleared by addressing the CLIRQ command
register or by holding ON low for 50ms.
Table 15. Interrupt Request Status Register
STATUS
REGISTER[BIT] VALUE IRQSTAT REGISTER BIT MEANING
IRQSTAT [0] 0
1
Pushbutton Status Active (Real Time)
IRQSTA
T [1] 0
1
Hard Reset Occurred
IRQSTA
T [2] 0
1
PGOOD Timeout Occurred
IRQSTA
T [3] 0
1
Undervoltage Warning
IRQSTA
T [4] 0
1
Undervoltage Standby Occurred
IRQSTA
T [5] 0
1
Overtemperature Warning
IRQSTA
T [6] 0
1
Overtemperature Standby Occurred
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

LTC3676IUJ-1#TRPBF

Mfr. #:
Buy LTC3676IUJ-1#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Pwr M Solution for Application Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet