LTC3676IUJ-1#TRPBF Datasheet LTC3676HUJ#PBF, LTC3676HUJ-1#PBF, LTC3676ELXE-1#PBF | P25-P27

LTC3676/LTC3676-1

3676fe

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OPERATION

IRQSTAT and MSKIRQ Registers

The bits in the MSKIRQ command register are set to mask

warning, fault, and pushbutton status reporting to the IRQ

pin. When set to mask, the IRQ pin is not pulled low as a

result of a fault or warning. Even though the IRQ pin is not

pulled low the masked bit is set in the IRQSTAT register.

When undervoltage, overtemperature faults, and hard

reset signals are masked, the IRQ pin is not pulled low

but LTC3676 state controller is pushed into the STANDBY

or POR/HRST state. Accessing the CLIRQ status register

clears the latched bits in the IRQSTAT status register and

releases the IRQ pin.

Table 16. Interrupt Request Mask Command Register

COMMAND

MSKIRQ [0] 0*

Pass Pushbutton Status

Mask Pushbutton Status

MSKIRQ [2] 0*

Pass PGOOD T

imeout

Mask PGOOD Timeout

MSKIRQ [3] 0*

Pass Under

voltage Warning

Mask Undervoltage Warning

MSKIRQ [4] 0*

Pass Under

voltage Shutdown

Mask Undervoltage Shutdown

MSKIRQ [5] 0*

Pass Overtemperature W

arning

Mask Overtemperature Warning

MSKIRQ [6] 0*

Pass Overtemperature Shutdown

Mask Overtemperature Shutdown

*denotes default power-on value.

IRQ and IRQSTAT are not cleared by hard reset or fault

shutdown. If V

remains applied while the LTC3676 is in

STANDBY or POR/HRST then IRQSTAT may be read on

the subsequent power up to determine if a fault or hard

reset occurred.

RSTO Status Pin

The LTC3676 RSTO status pin is pulled low when always-

on LDO1 is 8% below its programmed value or when the

LTC3676 is in the one second HRST timer state.

Hard Reset

A hard reset can be initiated by holding the ON pin low

or writing to the HRST command register. Bit six of the

CNTRL command register determines how long ON must

remain low to initiate the hard reset. A hard reset sets

all I

C command register bits to their default power-on

state. Table 17 shows the command register control of

hard reset function.

Table 17. Hard Reset Time Control Command Register

COMMAND

CNTRL[6] 0*

10 seconds

5 seconds

*denotes default power-on value.

A hard reset command will push the LTC3676 state con-

troller through

the 1 second HRST timer state and into

the POR/HRST state.

Fault Shutdown

An undervoltage or overtemperature fault will push the

LTC3676 state controller through the 1 second standby

timer state and into standby state. If a down sequence

is selected in the command registers, it will be executed

during the 1 second power down interval.

LTC3676-1 Operation

The LTC3676-1 option supports DDR memory operation

by generating a DDR termination reference and supply

rail equal to one-half the voltage applied to VDDQIN Pin 8.

An internal resistive divider creates a reference voltage of

one-half the voltage on VDDQIN. This reference is used

by the V

reference buffer to output one-half of VDDQIN

on VTTR Pin 9. The VTTR voltage is used as the reference

for 1.5A switching regulator 1 which is used as the DDR

termination supply. The LTC3676-1 EN_B1 pin and com

mand register

bit Buck1[7] enable both VTTR output and

switching regulator 1.

Figure 1 shows typical application connections for the

LTC3676-1 DDR termination reference and

termination

supply.

LDO4 has I

C command register selectable output volt-

ages of 1.2

V (default), 2.5V, 2.8V and 3V and is enabled

only using the I

C command register. Table 18 shows

the LDO4 command register controls for the LTC3676-1.

LTC3676/LTC3676-1

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OPERATION

Table 18. LDO4 Control Command Register Setting (LTC3676-1)

COMMAND

LDOB[0] 0*

Do Not Keep Alive LDO4 in Standby

Keep Alive LDO4 in Standby

LDOB[1]

Enable LDO4 at Any Output Voltage

Enable LDO4 Only if Output Voltage Is <300mV

LDOB[2] 0*

LDO4 Disabled

LDO4 Enable

LDOB[4:3]

00*

1.2V

2.5V

2.8V

3.0V

*denotes default power-on value.

C OPERATION

The LTC3676 communicates with a bus master using

the standard I

C 2-wire interface. The timing diagram in

Figure14 shows the relationship of the signals on the

bus. The two bus lines, SDA and SCL must be high when

the bus is not in use. External pull-up resistors or current

sources, such as the LTC1694 SMBus accelerator, are

required on SDA and SCL. The LTC3676 is both a slave

receiver and slave transmitter. The I

C control signals,

SDA and SCL are scaled internally to the DV

supply.

must be connected to the same power supply as

the bus pull-up resistors.

The I

C port has an undervoltage lockout on the DV

pin. When DV

is below approximately 1V, the I

serial port is cleared and the command registers are set

to default POR values.

The

complete I

C command register table is shown in

Table 20.

C Bus Speed

The I

C port operates at speeds up to 400kHz. It has

built in timing delays to ensure correct operation when

addressed from an I

C compliant master device. It also

contains input filters designed to suppress glitches should

the bus become corrupted.

C START and STOP Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3676, the master may transmit a STOP condition which

commands the LTC3676 to act upon its new command

set. A STOP condition is sent by the master by transition

ing SDA from LOW to HIGH while SCL is HIGH. The bus

is then free for communication with another I

C device.

C Byte Format

Each byte sent to or received from the LTC3676 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data

should be sent to the LTC3676

most significant bit (MSB) first.

C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3676 is written

to, it acknowledges its write address and subsequent data

bytes. When it is read from, the LTC3676 acknowledges

its read address only. The bus master should acknowledge

data returned from the LTC3676.

An acknowledge generated by the LTC3676 lets the master

know that the latest byte of information was received.

The master generates the acknowledge related clock and

releases the SDA line during the acknowledge clock cycle.

The LTC3676 pulls down the SDA line during the write

acknowledge clock pulse so that it is a stable LOW during

the HIGH period of this clock pulse.

At the end of a byte of data transferred from the LTC3676

during a READ operation, the LTC3676 releases the SDA

line to allow the master to acknowledge receipt of the

data. Failure of the master to acknowledge data from the

LTC3676 has no effect on the operation of the I

C port.

LTC3676/LTC3676-1

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OPERATION

C Slave Address

The LTC3676 responds to factory programmed read and

write addresses. The least significant bit of the address byte

is 0 when writing data and 1 when reading data. Table 19

shows read and write addresses for the LTC3676 options.

Table 19. LTC3676 and LTC3676-1 I

C Read and Write

Addresses

LT C PART NUMBER R/W ADDRESS

LTC3676 W 0111 1000, 0x78

LTC3676 R 0111 1001, 0x79

LTC3676-1 W 0111 1010, 0x7A

LTC3676-1 R 0111 1011, 0x7B

C Write Operation

The LTC3676 has twenty-two command registers for

control input. They are accessed by the I

C port via a

sub-addressed writing system.

A single write cycle of the LTC3676 consists of exactly

three bytes except when a clear interrupt or hard reset

command is written. The first byte is always the LTC3676

write address. The second byte represents the LTC3676

sub-address. The sub-address is a pointer which directs

the subsequent data byte within the LTC3676. The third

byte consists of the data to be written to the location

pointed to by the sub-address.

As shown in Figure 15, the LTC3676 supports multiple

sub-addressed write operations. Data pairs sent following

the chip write address are interpreted as sub-address and

data. Any number of sub-address and data pairs may be

sent. The data in the command registers is not acted on

by the LTC3676 until a STOP signal is issued.

The LTC3676 will keep interim writes to the registers

when

repeat START condition occurs. A repeat start may be

used to set up other devices on the I

C bus prior to send-

ing a STOP condition. The LTC3676 will act on the data

written

prior to the repeat start when a STOP condition

is detected.

C Read Operation

Figure 16 shows the LTC3676 command register read

sequence. The bus master reads a byte of data from a

LTC3676 command or status register by first writing the

LTC3676 write address followed by the sub-address to

be read from. The LTC3676 acknowledges each of the

two bytes. Next, the bus master initiates a new START

condition and sends the LTC3676 read address. Follow

ing the

acknowledge of the read address by the LTC3676,

the

LTC3676 pushes data onto the I

C bus for the 8 clock

cycles. The bus master then acknowledges the data on

its ninth clock.

The last read sub-address that is written to the LTC3676

is stored. This allows repeated polling of a command or

status register without the need to re-write its sub-address.

Additionally, the last register written may be immedi

ately read by issuing a START condition followed by read

address and clocking out the data.

Figure 14. LTC3676 I

C Serial Port Timing

SU, DAT

HD, STA

HD, DAT

SDA

SCL

SU, STA

HD, STA

SU, STO

3676 F14

BUF

LOW

HIGH

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

LTC3676IUJ-1#TRPBF

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Switching Voltage Regulators Pwr M Solution for Application Processor

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