LTC3676/LTC3676-1
34
3676fe
For more information www.linear.com/LTC3676
TYPICAL APPLICATIONS
LTC3676-1 PMIC Configured to Support Freescale i.MX6 Processor with DDR V
TT
and VTTR
2027
V
IN
3V TO 5.5V
LDO1
3V
25mA
WAKE
V
DDHIGH
ARM
28
26
36 35 16 15
10pF
22µF
22µF
22µF
22µF
178k 47µF
H
(1.37V)
(1.37V)
22
F
634k
200k
F
VDDARM_IN
VDDSOC_IN
VDD_DDR_IO
VSNVS_IN
VDDHIGH_INV
DDHIGH
ARM
0.9V TO 1.5V
AT 2.5A
FREESCALE
i.MX6
200k
68k
68k
4.7k4.7k
68k68k
31
10pF
10pF
178k 47µF
1.5µH
25
200k
215k
200k
11
47µF
H
23
SOC
0.9V TO 1.5V
AT 1.5A
40
10pF
215k 47µF
H
24
0.047µF
DDR
1.5V AT 2.5A
VTT
0.75V AT 1.5A
SW3V
IN
LDO1
FB_L1
RSTORSTO
I/O
WAKE
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
FB_B3
SW2
FB_B2
SW4
FB_B4
SW1
FB_B1
VDDQIN
8
VTTR
9
F
LDO3
1.8V
300mA
LDO3
4
F
V
DDHIGH
2.97V
300mA
619k
200k
3676 TA03
41
LDO2
FB_L2
GND
LTC3676-1
GND
DDR
8 CHIPS
WITH TERM
3
1
F
2
V
IN_L2
F
5
V
IN_L3
F
LDO4
3V
300mA
LDO4
6
F
7
V
IN_L4
PV
IN4
PV
IN3
PV
IN2
PV
IN1
33
37
34
18
17
30
10
38
IRQIRQ
32
PGOODPGOOD
SCL
39
SCL
14
SCA
SDA
13
VSTB
VSTB
19
PWR_ON
PWR_ON
21
ON
29
DV
DD
12
WAKE
SEQUENCE:
ARM
SOC
DDR
VTT
VDDHIGH
LDO3
LTC3676/LTC3676-1
35
3676fe
For more information www.linear.com/LTC3676
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
6.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
0.40 ±0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
4.42 ±0.05
4.42 ±0.05
0.75 ±0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.50 ±0.05
(4 SIDES)
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
LTC3676/LTC3676-1
36
3676fe
For more information www.linear.com/LTC3676
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
LXE48 (AA) LQFP 0416 REV A
0° – 7°
11° – 13°
0.45 – 0.75
1.00 REF
11° – 13°
1
48
1.60
MAX
1.35 – 1.45
0.05 – 0.150.09 – 0.20
0.50
BSC
0.17 – 0.27
GAUGE PLANE
0.25
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY
SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED
PAD, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
R0.08 – 0.20
7.15 – 7.25
5.50 REF
1
36
25
12
5.50 REF
7.15 – 7.25
48
13 24
37
C0.30
PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
SIDE VIEW
SECTION A – A
0.50 BSC
0.20 – 0.30
1.30 MIN
9.00 BSC
A A
7.00 BSC
1
12
7.00 BSC
4.15 ±0.10
4.15 ±0.10
9.00 BSC
48 37
1324
37
13 24
36 36
25
25
SEE NOTE: 3
C0.30 – 0.50
4.15 ±0.05
4.15
±0.05
C0.30
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG #05-08-1927 Rev A)
Exposed Pad Variation AA
12

LTC3676IUJ-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Pwr M Solution for Application Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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