LTC3676/LTC3676-1
16
3676fe
For more information www.linear.com/LTC3676
Figure 2. LDO1, LDO2 and LDO4 Application Circuit
OPERATION
LTC3676 Resistor Programmable LDO2 and LDO4
LDO2 and LDO4 output voltages are programmed by resis-
tor dividers
tied from the LDO output pin to the feedback
pin
as shown in Figure 2. The output voltage is calculated
using the following formula:
V
LDO
= 725 1+
R1
R2
mV
( )
output is 1.2V with selectable outputs of 2.5V, 2.8V, and
3.0V. LDO4 is enabled only through the command register
bit LDOB[2].
LDO4 Command Register Controls
Table 3. LDO4 Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
LDOB[0] 0*
1
Do Not Keep Alive LDO4 in Standby
Keep Alive LDO4 in Standby
LDOB[1]
0*
1
Enable LDO4 at Any Output V
oltage
Enable LDO4 Only if Output Voltage is <300mV
LDOB[2]
(LTC3676)
0*
1
LDO4 Disabled if EN_L4 is Low
LDO4 Enabled
LDOB[2]
(LTC3676-1)
0*
1
LDO4 Disabled
LDO4 Enabled
LDOB[4:3]
(LTC3676-1)
00*
LDO4 Output = 1.2V
LDOB[4:3]
(LTC3676-1)
01 LDO4 Output = 2.5V
LDOB[4:3]
(LTC3676-1)
10 LDO4 Output = 2.8V
LDOB[4:3]
(LTC3676-1)
11 LDO4 Output = 3V
*denotes default power-on value.
STEP-DOWN SWITCHING REGULATORS
The LTC3676 contains four buck regulators. Tw o of the
buck regulators are capable of delivering up to 2.5A load
current and the other two can deliver up to 1.5A each. The
regulators have forward and reverse current limiting, soft-
start, and switch slew rate control for lower radiated EMI.
The LTC3676 buck regulators are capable of 100% duty
cycle, or dropout, regulation. When in dropout the regulator
output voltage is equal to PV
IN
minus the load current times
R
DS(ON)
of the converters PMOS device and inductor DCR.
Each buck regulator is enabled using its enable pin or I
2
C
command register control. Operating modes, start-up op-
tion, reference
voltage, and switch slew rate are controlled
using the I
2
C port.
The buck converter I
2
C command register controls are
shown in Table 4, Table 5, Table 6, and Table 7.
+
V
IN
LDO
FB
R1
R2
3676 F02
F
0.725V
Fixed Output LDO3
Regulator LDO3 has a fixed voltage output of 1.8V.
Table 2. LDO2 and LDO3 Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
LDOA[0] 0*
1
Do Not Keep Alive LDO2 in Standby
Keep Alive LDO2 in Standby
LDOA[1]
0*
1
Enable LDO2 at Any Output V
oltage
Enable LDO2 Only if Output Voltage is <300mV
LDOA[2] 0*
1
LDO2 Disabled if EN_L2 is Low
LDO2 Enable
LDOA[3]
0*
1
Do Not Keep Alive LDO3 in Standby
Keep Alive LDO3 in Standby
LDOA[4]
0*
1
Enable LDO3 at Any Output V
oltage
Enable LDO3 0nly if Output Voltage is <300mV
LDOA[5] 0*
1
LDO3 Disabled if EN_L3 is Low
LDO3 Enabled
*denotes default power-on value.
LDO4 Operation LTC3676-1
LDO4 on the LTC3676-1 has neither enable nor feedback
pins. There are four LDO4 output voltages selectable by
command register bits LDOB[4:3]. The power-on default
LTC3676/LTC3676-1
17
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For more information www.linear.com/LTC3676
OPERATION
Operating Modes
The buck regulators can operate in either pulse-skipping,
Burst Mode operation, or forced continuous mode. In
pulse-skipping setting the regulator will skip pulses at
light loads but will operate at constant frequency. In Burst
Mode setting the regulator operates in Burst Mode opera
-
tion at light loads and in constant frequency PWM mode
at higher load. In forced continuous setting the inductor
current is allowed to be less than zero over the full range
of duty cycles. In forced continuous operation the buck
regulator has the ability to sink output current. Because
the regulator is switching every cycle regardless of output
load, forced continuous mode results in the least output
voltage ripple at light load.
Output Voltage Programming
Each of the step-down converters uses a dynamically slew
-
ing DAC for its reference. The output voltage of the DAC
reference
is selectable using a 5-bit I
2
C command register.
The output voltage is set by using a resistor divider con-
nected from
the step-down switching regulator output to
its
feedback pin as shown in Figure 3. The output voltage
is calculated using the following formula:
V
OUT
= 1+
R1
R2
DVBx 12.5 + 412.5
( )
mV
( )
DVBx is the decimal value of the 5-bit binary number in
the I
2
C command registers. The default DAC input code is
11001 (25 in decimal) which corresponds to a reference
voltage of 725mV. Typical values for R1 are in the range
of 40k to 1M. Capacitor C
FB
cancels the pole created by
the feedback resistors and the input capacitance on the
FB pin and helps to improve load step transient response.
A value of 10pF is recommended.
Inductor Selection
The choice of step-down switching regulator inductor
influences the efficiency and output voltage ripple of the
converter. A larger inductor improves efficiency since the
peak current is closer to the average output current. Larger
inductors generally have higher series resistance that
counters the efficiency advantage of reduced peak current.
Inductor ripple current is a function of switching frequency,
inductance, V
IN
, and V
OUT
as shown in this equation:
ΔI
L
=
1
f L
V
OUT
1
V
OUT
V
IN
A good starting design point is to use an inductor that
gives ripple equal to 30% output current. Select an induc-
tor with
a DC current rating at least 1.5 times larger than
the
maximum load current to ensure the inductor does
not saturate.
Input and Output Capacitor Selection
Low ESR ceramic capacitors should be used at both the
output and input supply of the switching regulators. Only
X5R or X7R ceramic capacitors should be used since they
have better temperature and voltage stability than other
ceramic types.
Operating Frequency
The switching frequency of each of the LTC3676 switching
regulators may be set using the I
2
C command registers.
The default switching frequency is 2.25MHz and the select-
able frequency
is 1.125MHz. Operation at lower frequency
improves efficiency by reducing internal gate charge and
switching losses at the expense of a larger inductor.
The lowest duty cycle of the step-down converter is de
-
termined by minimum on-time. Minimum on-time is the
shortest
time duration that the converter can turn its top
PMOS on and off again. The time is the sum of gate charge
Figure 3. Step-Down Switching Regulator Application Circuit
DEFAULT
725mV
DAC
5
SW
FB
MODE
EN
C
FB
R1
C
OUT
R2
3676 F03
PV
IN
PWM
CONTROL
2
LTC3676/LTC3676-1
18
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For more information www.linear.com/LTC3676
Figure 4. Phase Settings Full- and Half-Speed Buck Clock
OPERATION
time plus internal delays of the peak current sense and
PWM control. If the converters duty cycle will be 20% or
less at 2.25MHz it is recommended to use the 1.125MHz
setting to avoid minimum duty cycle. If the duty cycle falls
below the minimum on-time of the converter, the output
voltage ripple will increase as the converter skips cycles.
The default setting for the LTC3676-1 Buck1 switching
frequency is 1.125MHz to ensure minimum on time ef
-
fects are
avoided at DDR termination reference voltages.
Phase Selection
To
reduce the cycle by cycle peak current drawn by the
switching regulators, the clock phase at which each of the
LTC3676 buck’s PMOS switch turns on can be set using
I
2
C command register settings.
Table 4. Buck1 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK1[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK1[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK1[2]
(LTC3676)
0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK1[2]
(LTC3676-1)
0*
1
Switching Frequency 1.125MHz
Switching Frequency 2.25MHz
BUCK1[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK1[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK1[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK1[7] 0*
1
Buck1 Disabled if EN_B1 Pin Is Low
Buck1 Enabled
*denotes default power on-value.
Table 5. Buck2 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK2[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK2[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK2[2] 0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK2[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK2[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK2[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK2[7] 0*
1
Buck2 Disabled if EN_B2 Pin Is Low
Buck2 Enabled
*denotes default power-on value.
2.25MHz
φ1 φ2 φ1
1.125MHz
3676 F04
φ1 φ2
Switch Slew Rate Control
To help reduce EMI the switch rise time of each buck regula-
tor is
slew limited by default. A faster setting is selectable
using
the I
2
C buck command registers. The faster setting
will improve efficiency if limited edge rate is not required.
Soft-Start
To reduce inrush current at start-up each buck regulator
soft starts when enabled. When enabled the internal ref
-
erence voltage is ramped from ground to the level of the
slewing
DAC output at a rate of 0.8V/ms. During soft-start
the converter is forced to pulse-skipping mode regardless
of command register mode settings.

LTC3676IUJ-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Pwr M Solution for Application Processor
Lifecycle:
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