P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 12 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Figure 14 shows that P82B96 can achieve high clock rates over long cables. While
calculating with lumped wiring capacitance yields reasonable approximations to actual
timing, even 25 meters of cable is better treated using transmission line theory. Flat ribbon
cables connected as shown, with the bus signals on the outer edge, will have a
characteristic impedance in the range 100 Ω to 200 Ω. For simplicity they cannot be
terminated in their characteristic impedance but a practical compromise is to use the
minimum pull-up allowed for P82B96 and place half this termination at each end of the
cable. When each pull-up is below 330 Ω, the rising edge waveforms have their first
voltage ‘step’ level above the logic threshold at Rx and cable timing calculations can be
based on the fast rise/fall times of resistive loading plus simple one-way propagation
delays. When the pull-up is larger, but below 750 Ω, the threshold at Rx will be crossed
after one signal reflection. So at the sending end it is crossed after 2 times the one-way
propagation delay and at the receiving end after 3 times that propagation delay. For flat
cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays will be about 5 ns per meter. The 10 % to 90 % rise and fall times on
the cable will be between 20 ns and 50 ns, so their delay contributions are small. There
will be ringing on falling edges that can be damped, if required, by using Schottky diodes
as shown.
When the Master SCL HIGH and LOW periods can be programmed separately, for
example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow
for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns
plus the net delay in the slave's response data signal caused by bus and buffer delays.
The longest data delay is the sum of the delay of the falling edge of SCL from master to
slave and the delay of the rising edge of SDA from slave data to master. Because the
buffer will ‘stretch’ the programmed SCL LOW period, the actual SCL frequency will be
lower than calculated from the programmed clock periods. In the example for 25 meters
the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising
edge is delayed 570 ns. The required additional LOW period is
(490 ns + 570 ns) = 1060 ns and the I
2
C-bus specifications already include an allowance
for a worst case bus rise time 0 % to 70 % of 425 ns. (The bus rise time can be 300 ns
30 % to 70 %, which means it can be 425 ns 0 % to 70 %. The 25 meter cable delay times
as quoted already include all rise and fall times.) Therefore, the microcontroller only needs
to be programmed with an additional (1060 ns − 400 ns − 425 ns) = 235 ns, making a
total programmed LOW period 1535 ns. The programmed LOW will the be stretched by
400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH
period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
Note that in both the 100 meter and 250 meter examples, the capacitive loading on the
I
2
C-buses at each end is within the maximum allowed Standard mode loading of 400 pF,
but exceeds the Fast mode limit. This is an example of a ‘hybrid’ mode because it relies on
the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings
with rise times that contribute significantly to the system delays. The cables cause large
propagation delays, so these systems need to operate well below the 400 kHz limit, but
illustrate how they can still exceed the 100 kHz limit provided all parts are capable of
Fast mode operation. The fastest example illustrates how the 400 kHz limit can be
exceeded, provided masters and slaves have the required timings, namely smaller than
the maximum allowed for Fast mode. Many NXP slaves have delays shorter than 600 ns
and all Fm+ devices must be < 450 ns.
