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P82B96TD/S900,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 7 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Input logic switching threshold voltages
V
Sx
, V
Sy
input logic voltage LOW on normal I
2
C-bus
[4]
- 640 600 (see Figure 7)mV
V
Sx
, V
Sy
input logic level HIGH
threshold
on normal I
2
C-bus
[4]
700 650 - (see Figure 8)mV
dV
Sx
/dT,
dV
Sy
/dT
temperature coefficient
of input thresholds
- −2 - - - mV/K
V
Rx
, V
Ry
input logic HIGH level fraction of applied V
CC
0.58V
CC
- - 0.58V
CC
-V
V
Rx
, V
Ry
input threshold fraction of applied V
CC
- 0.5V
CC
---V
V
Rx
, V
Ry
input logic LOW level fraction of applied V
CC
- - 0.42V
CC
- 0.42V
CC
V
Logic level threshold difference
V
Sx
, V
Sy
input/output logic level
difference
V
Sx
output LOW at
0.2 mA − V
Sx
input
HIGH maximum
[2]
50 85 - 50 - mV
Thermal resistance
R
th(j-pcb)
thermal resistance from
junction to printed-circuit
board
SOT96-1 (SO8);
average lead
temperature at board
interface
- 127 - - - K/W
Bus release on V
CC
failure
V
Sx
, V
Sy
,
V
Tx
, V
Ty
V
CC
voltage at which all
buses are guaranteed to
be released
- - 1 (see Figure 9)V
dV/dT temperature coefficient
of guaranteed release
voltage
- −4 - - - mV/K
Buffer response time
[5]
T
fall delay
V
Sx
to V
Tx
,
V
Sy
to V
Ty
buffer time delay on
falling input between
V
Sx
= input switching
threshold, and V
Tx
output falling 50 %
R
Tx
pull-up = 160 Ω;
no capacitive load;
V
CC
=5V
-70- - -ns
T
rise delay
V
Sx
to V
Tx
,
V
Sy
to V
Ty
buffer time delay on
rising input between
V
Sx
= input switching
threshold, and V
Tx
output reaching 50 %
V
CC
R
Tx
pull-up = 160 Ω;
no capacitive load;
V
CC
=5V
-90- - -ns
Table 5. Characteristics
…continued
T
amb
= +25
°
C; voltages are specified with respect to GND with V
CC
= 5 V, unless otherwise specified.
Symbol Parameter Conditions T
amb
= +25 °C T
amb
= −40 °C to
+125 °C
[1]
Unit
Min Typ Max Min Max
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 8 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
[1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.
[2] The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for V
Sx
output LOW will always exceed
the minimum V
Sx
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC.
While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because
the resulting system would be very susceptible to induced noise and would not support all I
2
C-bus operating modes.
[3] The output logic LOW depends on the sink current. For scaling, see
Application Note AN255
.
[4] The input logic threshold is independent of the supply voltage.
[5] The fall time of V
Tx
from 5 V to 2.5 V in the test is approximately 15 ns.
The fall time of V
Sx
from 5 V to 2.5 V in the test is approximately 50 ns.
The rise time of V
Tx
from 0 V to 2.5 V in the test is approximately 20 ns.
The rise time of V
Sx
from 0.9 V to 2.5 V in the test is approximately 70 ns.
T
fall delay
V
Rx
to
V
Sx
, V
Ry
to V
Sy
buffer time delay on
falling input between
V
Rx
= input switching
threshold, and V
Sx
output falling 50 %
R
Sx
pull-up = 1500 Ω;
no capacitive load;
V
CC
=5V
- 250 - - - ns
T
rise delay
V
Rx
to
V
Sx
, V
Ry
to V
Sy
buffer time delay on
rising input between
V
Rx
= input switching
threshold, and V
Sx
output reaching 50 %
V
CC
R
Sx
pull-up = 1500 Ω;
no capacitive load;
V
CC
=5V
- 270 - - - ns
Input capacitance
C
i
input capacitance effective input
capacitance of any
signal pin measured
by incremental bus
rise times
--7 - 7pF
Table 5. Characteristics
…continued
T
amb
= +25
°
C; voltages are specified with respect to GND with V
CC
= 5 V, unless otherwise specified.
Symbol Parameter Conditions T
amb
= +25 °C T
amb
= −40 °C to
+125 °C
[1]
Unit
Min Typ Max Min Max
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 9 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
V
OL
at Sx typical and limits over temperature
(1) Maximum
(2) Typical
(3) Minimum
V
OL
at Sx typical and limits over temperature
(1) Maximum
(2) Typical
(3) Minimum
Fig 5. V
OL
as a function of junction temperature
(I
OL
= 0.2 mA)
Fig 6. V
OL
as a function of junction temperature
(I
OL
= 3 mA)
V
IL(max)
at Sx changes over temperature range V
IH(min)
at Sx changes over temperature range
Fig 7. V
IL(max)
as a function of junction temperature Fig 8. V
IH(min)
as a function of junction temperature
Fig 9. V
CC(max)
that guarantees bus release limit over temperature
600
800
1000
V
OL
(mV)
400
T
j
(°C)
002aac069
(1)
(3)
−50 1251007550250−25
(2)
1200
V
OL
(mV)
400
T
j
(°C)
002aac070
(1)
(3)
(2)
1000
800
600
−50 1251007550250−25
1000
V
IL(max)
(mV)
200
T
j
(°C)
002aac071
800
600
400
−50 1251007550250−25
1000
V
IH(min)
(mV)
200
T
j
(°C)
002aac072
800
600
400
−50 1251007550250−25
600
1400
V
CC(max)
(mV)
400
T
j
(°C)
002aac075
−50 1251007550250−25
800
1000
1200
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P82B96TD/S900,118

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Buy P82B96TD/S900,118
Manufacturer:
NXP Semiconductors
Description:
Interface - Signal Buffers, Repeaters Dual bidirectional Bus buffer
Lifecycle:
New from this manufacturer.
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