P82B96TD/S900,118 Datasheet P82B96TD/S900,118, P82B96DP,118, P82B96TD,118 | P16-P18

Product data sheet Rev. 08 — 10 November 2009 16 of 32

NXP Semiconductors

P82B96

Dual bidirectional bus buffer

Figure 15, Figure 16, and Figure 17 show the P82B96 used to drive extended bus wiring,

with relatively large capacitance, linking two Fast mode I

C-bus nodes. It includes

simpliﬁed expressions for making the relevant timing calculations for 3.3 V or 5 V

operation. Because the buffers and the wiring introduce timing delays, it may be

necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the

actual bus frequency will be lower than the nominal Master timing due to bit-wise

stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed are:

A — The propagation delay of the master signal through the buffers and wiring to the

slave. The important delay is that of the falling edge of SCL because this edge ‘requests’

the data or acknowledge from a slave. See Figure 15.

B — The effective stretching of the nominal LOW period of SCL at the master caused by

the buffer and bus rise times. See Figure 16.

C — The propagation delay of the slave's response signal through the buffers and wiring

back to the master. The important delay is that of a rising edge in the SDA signal. Rising

edges are always slower and are therefore delayed by a longer time than falling edges.

(The rising edges are limited by the passive pull-up while falling edges are actively driven).

See Figure 17.

The timing requirement in any I

C-bus system is that a slave's data response (which is

provided in response to a falling edge of SCL) must be received at the master before the

end of the corresponding LOW period of SCL as appears on the bus wiring at the master.

Since all slaves will, as a minimum, satisfy the worst case timing requirements of a

400 kHz part, they must provide their response within the minimum allowed clock LOW

period of 1300 ns. Therefore in systems that introduce additional delays it is only

necessary to extend that minimum clock LOW period by any ‘effective’ delay of the slave's

response. The effective delay of the slaves response equals the total delays in SCL falling

Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.

C = F; R = Ω.

Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times

P82B96 P82B96

SDA

local master bus

CCM

SDA

MASTER

C-BUS

slave bus

capacitance

buffered bus

wiring capacitance

master bus

capacitance

GND (0 V)

CCB

buffered expansion bus

Tx/Rx

Tx/Rx Sx

Rb Rs

C-BUS

SLAVE

CCS

remote slave bus

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Product data sheet Rev. 08 — 10 November 2009 17 of 32

NXP Semiconductors

P82B96

Dual bidirectional bus buffer

edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of

the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on

SDA, reaching the master (Figure 17).

The master microcontroller should be programmed to produce a nominal SCL LOW

period = (1300 + A − B + C) ns, and should be programmed to produce the nominal

minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle

time is not shorter than the minimum 2500 ns. If found necessary, just increase either

clock period.

Due to clock stretching, the SCL cycle time will always be longer than

(600+1300+A+C)ns.

Example:

The master bus has an RmCm product of 100 ns and V

CCM

=5V.

The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 Ω to 5 V giving

an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to

≥ (1300 + 372.5 − 482 + 472) ns, that is ≥ 1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.

The nominal microcontroller clock period will be ≥ (1662.5 + 600) ns = 2262.5 ns,

equivalent to a frequency of 442 kHz.

The actual bus clock period, including the 482 ns clock stretch effect, will be below

(nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable

frequency of 364 kHz.

Fig 18. I

C-bus multipoint application

P82B96

SDA

SCL

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12 V

3.3 V to 5 V

P82B96

Sx Sy

SCL/SDA

P82B96

Sx Sy

SCL/SDA

P82B96

Sx Sy

SCL/SDA

P82B96

Sx SCL

Sy SDA

no limit to the number of connected bus devices

twitsted-pair telephone wires,

USB, or flat ribbon cables;

up to 15 V logic levels,

include V

and GND

3.3 V 3.3 V

Product data sheet Rev. 08 — 10 November 2009 18 of 32

NXP Semiconductors

P82B96

Dual bidirectional bus buffer

10.2 Negative undershoot below absolute minimum value

The reason why the IC pin reverse voltage on pins Tx and Rx in Table 4 “Limiting values”

is speciﬁed at such a low value, −0.3 V, is not that applying larger voltages is likely to

cause damage but that it is expected that, in normal applications, there is no reason why

larger DC voltages will be applied. This ‘absolute maximum’ speciﬁcation is intended to be

a DC or continuous ratings and the nominal DC I

C-bus voltage LOW usually does not

even reach 0 V. Inside P82B96 at every pin there is a large protective diode connected to

the GND pin and that diode will start to conduct when the pin voltage is more than about

−0.55 V with respect to GND at 25 °C ambient.

Figure 21 shows the measured characteristic for one of those diodes inside P82B96. The

plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor,

so the pulse durations are long duration (several milliseconds) and are reaching peaks of

over 2 A when more than −1.5 V is applied. The IC becomes very hot during this testing

but it was not damaged. Whenever there is current ﬂowing in any of these diodes it is

possible that there can be faulty operation of any IC. For that reason we put a speciﬁcation

on the negative voltage that is allowed to be applied. It is selected so that, at the highest

allowed junction temperature, there will be a big safety factor that guarantees the diode

will not conduct and then we do not need to make any 100 % production tests to

guarantee the published speciﬁcation.

For the P82B96, in speciﬁc applications, there will always be transient overshoot and

ringing on the wiring that can cause these diodes to conduct. Therefore we designed the

IC to withstand those transients and as a part of the qualiﬁcation procedure we made

tests, using DC currents to more than twice the normal bus sink currents, to be sure that

the IC was not affected by those currents. For example, the Tx/Ty and Rx/Ry pins were

tested to at least −80 mA which, from Figure 21, would be more than −0.8 V. The correct

functioning of the P82B96 is not affected even by those large currents. The Absolute

Maximum (DC) ratings are not intended to apply to transients but to steady state

conditions. This explains why you will never see any problems in practice even if, during

transients, more than −0.3 V is applied to the bus interface pins of P82B96.

Frequency = 624 kHz Ch1 frequency = 624 kHz

Fig 19. Propagation Sx to Tx (Sx pull-up to 5 V;

Tx pull-up to V

=10V)

Fig 20. Propagation Rx to Sx (Sx pull-up to 5 V;

Rx pull-up to V

=10V)

−2

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0 20001600800 1200400

−2

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0 20001600800 1200400

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P82B96TD/S900,118

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NXP Semiconductors

Description:

Interface - Signal Buffers, Repeaters Dual bidirectional Bus buffer

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P82B96TD/S900,118

P82B96TD/S900,118

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