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P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 14 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Table 6. Examples of bus capability
Refer to Figure 14.
+V
CC1
+V
cable
+V
CC2
R1
(Ω)
R2
(Ω)
C2
(pF)
Cable
length
Cable
capacitance
Cable
delay
Set master nominal SCL Effective
bus clock
speed
Maximum slave
response delay
HIGH period LOW period
5 V 12 V 5 V 750 2.2 k 400 250 m n/a
(delay based)
1.25 µs 600 ns 4000 ns 120 kHz Normal spec.
400 kHz parts
5 V 12 V 5 V 750 2.2 k 220 100 m n/a
(delay based)
500 ns 600 ns 2600 ns 185 kHz Normal spec.
400 kHz parts
3.3 V 5 V 3.3 V 330 1 k 220 25 m 1 nF 125 ns 600 ns 1500 ns 390 kHz Normal spec.
400 kHz parts
3.3 V 5 V 3.3 V 330 1 k 100 3 m 120 pF 15 ns 600 ns 1000 ns 500 kHz 600 ns
