1/40
TDA7500A
December 2001
FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
SOFTWARE AM/FM, AUDIO AND SOUND-
PROCESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC (4ADCs, 6DACs)
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE
(SAI)
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE (EMI)
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
12x2 MULTIFUNCTION GENERAL PURPOSE
I/O PORTS
DESCRIPTION
The TDA7500A is an integrated circuit implementing
a fully digital, integrated and advanced solution to
perform the signal processing in front of the power
amplifier and behind the AM/FM tuner or any other
audio source. The chip integrates two 45 MIPs DSP
cores: one for stereo decoding, noise blanking, weak
signal processing and multipath detection and one
for
sound processing, Dolby B, echo and noise cancel-
ling for the telephone.
TQFP100 (with slug down)
ORDERING NUMBER: TDA7500A
DIGITAL AM/FM SIGNAL PROCESSOR
BLOCK DIAGRAM
X Ram 1024
Y Ram 1024
P Ram 2048
P Rom 256
2
DSP1 Orpheus Core
FM processing,
AM processing,
Traffic memorization
Xchg
Interf.
P Ram 5632
P Rom 512
Y Ram 1024
Int
Reset
4
VDD
GND
4
DSP0 Orpheus Core
Audio processing,
Sound processing,
Debug Interface
4
ADCVDD
ADCGND
Debug Interface
ADC-ref
X Ram 1024
including 12 GPIO´s including12GPIO´s
Tes t
Grp & blk
sync., error
correction
4
RDS
Filter
SPI
Demod.
PLL Clock
Generator
8+3
External Memory Interface
SRAM 4Mx8
DRAM 128kx4
17
Noise & Echo Canc.
Dolby B
SPDIF 2ch.
Interface
2ch Sample
Rate
Converter
SAI 6ch.
Receiver
2
SAI Transmitter
2
3
4
4
10 word SPI 1
receive stack
4
SPI 2
IIC / SPI 1
6 Ch. Audio Bus
receive bit&word clk
digital audio in
SPDIF audio in
6 Channel
Audio Bus
λ
Pcontrol
Display
λ
P
Σ∆
DAC-ref
Oversampl.
Filter
Oversampl.
Filter
Oversampl.
Filter
Noise
Shaper
Noise
Shaper
Noise
Shaper
SC
Filter
Decimation
Filter
Decimation
Filter
CLK in
Crystal
Oscillator
RDS
Error corr. RDS blocks
or RDS clk, dat, qual
RDS bit/blk Int.
RDS SPI
analog in
Σ∆ Σ∆ Σ∆
SC
Filter
SC
Filter
SC
Filter
SC
Filter
SC
Filter
analog audio out
AVDD
AGND
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
TDA7500A
2/40
DESCRIPTION
(continued)
An I
2
C/SPI interface is implemented for control and communication with the main micro. A separate SPI is avail-
able to interface the display micro.The DSP cores are integrated with their associated data and program mem-
ories. The peripherals and interfaces I
2
C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory
Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled by
DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to
and controlled by DSP1. An hardware RDS filter , demodulator and decoder block is also embedded. No support
is needed from the DSPs but at initialisation so that RDS can work in background and in parallel with other DSP
processing. Separated Debug and Test Interfaces are connected to both DSP cores.
The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks
to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also
available.
The flexibility allowed by the wide memory space and by the two powerfull DSP cores make the TDA7500A us-
able for different applications. In example, inside the main radio as an audio co-processor or to perform the sig-
nal processing and equalisation associated to a digital power amplifier.
ABSOLUTE MAXIMUM RATINGS
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
THERMAL DATA
Note: 1. In still air
2. On 4 layers board with soldered slug
3. Measured on top side of the package
Symbol Parameter Value Unit
V
DD
V
CC
Power supplies Digital
Analog
-0.5 to +4.6
-0.5 to +4.6
V
V
V
aio
Analog Input and Output Voltage -0.5 to (V
CC
+0.5) V
V
dio
Digital Input and Output Voltage -0.5 to (V
DD
+0.5) V
V
di5
Digital Input Voltage (5V tolerant) -0.5 to 6.5 V
T
j
Operating Junction Temperature Range -40 to 125 °C
T
stg
Storage Temperature -55 to 150 °C
Symbol Parameter Value Unit
R
th j-amb
Thermal resistance junction to ambient
(1)
45 °C/W
Thermal resistance junction to ambient
(2)
20 °C/W
R
th j-case
Thermal junction to case
(3)
5 °C/W
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
3/40
TDA7500A
PIN DESCRIPTION
Name Type Description
1 GND1 Ground pin dedicated to the digital circuitry.
2 VDD1 Supply pin dedicated to the digital circuitry.
3 TESTEN I Test Enable (Input). When low, puts the chip into test mode and
muxes the XTI clock to all flip-flops. When TEST_SE is also
active, the scan chain shifting is enabled. To be connected to
Vdd in operating mode.
4 TESTSE I SCAN Enable (Input). When high with TESTEN also active,
controls the shifting of the internal scan chains. When active with
TESTEN not active, sets all tri-state outputs into hi-impedance
mode. To be connected to GND in operating mode.
5 NRESET I System Reset (Input). A low level applied to NRESET input
initializes the IC.
6 SCKM/DSP0_GPIO0 I/O
I
2
C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/
General Purpose I/O (Input/Output). Clock line for I
2
C bus. If SPI
interface is enabled, behaves as SPI bit clock. Optionally it can
be used as general purpose I/O controlled by DSP0.
7 MISOM/DSP0_GPIO1 I/O
I
2
C Serial Data Line (Input/Output)/SPI Master Input Slave
Output Serial Data (Input/Output)/General Purpose I/O (Input/
Output). Data line for I
2
C bus. If SPI is enabled, behaves as
Serial Data Input when in SPI Master Mode and Serial Data
Output when in SPI Slave Mode. Optionally it can be used as
general purpose I/O controlled by DSP0.
8 MOSIM/DSP0_GPIO2 I/O SPI Master Output Slave Input Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Serial Data Output when in
SPI Master Mode and Serial Data Input when in SPI Slave
Mode. Optionally it can be used as general purpose I/O
controlled by DSP0.
9 SSM/DSP0_GPIO3 I SPI Slave Select (Input)/General Purpose I/O (Input/Output). If
SPI is enabled, behaves as Slave Select line for SPI bus.
Optionally it can be used as general purpose I/O controlled by
DSP0.
10 SCKD/DSP0_GPIO4 I SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit
clock. Optionally it can be used as general purpose I/O
controlled by DSP0.
11 MISOD/DSP0_GPIO5 I/O SPI Master Input Slave Output Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Behaves as Serial Data
Input when in SPI Master Mode and Serial Data Output when in
SPI Slave Mode. Optionally it can be used as general purpose I/
O controlled by DSP0.
12 MISOD/DSP0_GPIO6 I/O SPI Master Output Slave Input Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Serial Data Output when in
SPI Master Mode and Serial Data Input when in SPI Slave
Mode. Optionally it can be used as general purpose I/O
controlled by DSP0.
13 SSD/DSP0_GPIO7 I SPI Slave Select (Input)/General Purpose I/O (Input/Output).
Behaves as Slave Select line for SPI bus. Optionally it can be
used as general purpose I/O controlled by DSP0.
Obsolete Product(s) - Obsolete Product(s)

TDA7500A

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet