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TDA7500A

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TDA7500A
60
SDO<2>/SRA<18>/DSP1_GPIO<7>
O SAI Outputs (Output)/EMI SRAM Address Line<18> (Output)/
General Purpose I/O (Input/Output). One stereo channel SAI
data output in SAI mode. EMI address line 18 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
61 SDO<0>/SRA<19> O SAI Output (Output)/EMI SRAM Address Line<19> (Output).
One stereo channel SAI data output in SAI mode. EMI address
line 19 in SRAM Mode.
62
SDI<2>/SRA<20>/DSP1_GPIO<6>
I SAI Input (Input)/EMI SRAM Address Line<20> (Output)/
General Purpose I/O (Input/Output). One stereo channel SAI
data input in SAI mode. EMI address line 20 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
63
SDI<1>/SRA<21>/RAS/DSP1_GPIO<5>
I SAI Input (Input)/EMI SRAM Address Line<21> (Output)/DRAM
Row Address Strobe (Output)/General Purpose I/O (Input/
Output). One stereo channel SAI data input in SAI mode. EMI
address line 21 in SRAM Mode. When in DRAM Mode this pin
acts as the row address strobe. Optionally it can be used as a
general purpose I/O.
64 SDI<0>/SRCCDC I SAI Input (Input)/SPDIF Input 3 (Input). One stereo channel SAI
data input in SAI mode. Stereo SPDIF input intended to connect
a digital audio source like a CD changer in SPDIF mode.
65 SCKT I/O SAI transmitter Bit Clock (Input/Output). SAI transmitter bit clock.
Master or slave.
66 LRCKT I/O SAI transmitter Left-Right Clock (Input/Output). SAI transmitter
Left-Right clock. Can be master or slave mode.
67 SCKR I SAI receiver Bit Clock (Input). SAI receiver bit clock. Slave only.
68 LRCKR I SAI receiver Left-Right Clock (Input/Output). SAI receiver Left-
Right clock. Slave only.
69 DBOUT1/DSP1_GPIO10 I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
70 DBIN1/OS10/DSP1_GPIO11 I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General
Purpose I/O (Input/Output). The serial data input for the Debug
Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Optionally it can
be used as a general purpose I/O.
71 DBCK1/OS11/DSP1_GPIO9 I/O Debug Port Bit Clock/Chip Status 1 (Input/Output)/General
Purpose I/O (Input/Output). The serial clock for the Debug Port
is provided when an input. When an output, together with OS0
provides information about the chip status. Optionally it can be
used as a general purpose I/O.
72 DBRQN1 I Debug Port Request Input (Input). Means of entering the Debug
mode of operation.
73 DBOUT0/DSP0_GPIO10 I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
N° Name Type Description
PIN DESCRIPTION
(continued)
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TDA7500A
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74 DBIN0/OS00/DSP0_GPIO11 I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General
Purpose I/O (Input/Output). The serial data input for the Debug
Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Optionally it can
be used as a general purpose I/O.
75 DBCK0/OS01/DSP0_GPIO9 I/O Debug Port Bit Clock/Chip Status 1 (Input/Output)/General
Purpose I/O (Input/Output). The serial clock for the Debug Port
is provided when an input. When an output, together with OS0
provides information about the chip status. Optionally it can be
used as a general purpose I/O.
76 DBRQN0 I Debug Port Request Input (Input). Means of entering the Debug
mode of operation.
77 VDD2 Supply pin dedicated to the digital circuitry.
78 GND2 Ground pin dedicated to the digital circuitry.
79 ADC<0> I Analog Inputs (Input). Single ended analog signal inputs to the
ADC.
80 ADC<1> I Analog Inputs (Input). Single ended analog signal inputs to the
ADC.
81 ADC<2> I Analog Inputs (Input). Single ended analog signal inputs to the
ADC.
82 ADC<3> I Analog Inputs (Input). Single ended analog signal inputs to the
ADC.
83 S2DREF I To be connected to ADCGND
84 ADCVDDREF I Voltage Reference (Input). Analog voltage reference input.
Signal is supplied by A354. (typical 3.3V).
85 ADCREF<2> I Voltage Reference (Input). External decoupling of the analog
references used for the sigma delta modulator.
86 ADCREF<1> I Voltage Reference (Input). External decoupling of the analog
references used for the sigma delta modulator.
87 ADCREF<0> I Voltage Reference (Input). External decoupling of the analog
references used for the sigma delta modulator.
88 ADCVDD Analog Supply pin dedicated to the A/D converter.
89 ADCGND Analog Ground pin dedicated to the A/D converter.
90 DAC<0> O Analog Outputs (Output). Analog signal outputs of the DAC
91 DAC<1> O Analog Outputs (Output). Analog signal outputs of the DAC
92 DAC<2> O Analog Outputs (Output). Analog signal outputs of the DAC
93 DAC<3> O Analog Outputs (Output). Analog signal outputs of the DAC
94 DAC<4> O Analog Outputs (Output). Analog signal outputs of the DAC
95 DAC<5> O Analog Outputs (Output). Analog signal outputs of the DAC
N° Name Type Description
PIN DESCRIPTION
(continued)
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TDA7500A
I/O DEFINITION AND STATUS
O: logic low output
X: undefined input/output
Z: high impedance
1: logic input output
96 DACREF<2> I Voltage Reference (Input). External decoupling of the analog
references of the CODEC and voltage biasing.
97 DACREF<1> I Voltage Reference (Input). It can be connected to pin 100.
98 DACREF<0> I Voltage Reference (Input). External decoupling of the analog
references of the CODEC and voltage biasing.
99 DACGND Analog Ground pin dedicated to the D/A converter.
100 DACVDD Analog Supply pin dedicated to the D/A converter.
Pin
#
Function
Reset
State
After Boot
I/O Comments
SPI
I
2
C
EMI
1 GND1 supply
2 VDD1 supply To be connected
to VDD
3 TESTEN X X X X input To be connected
to GND
4 TESTSE X X X X input Ext. Pulldown
5 NRESET X X X X input 5VT
6 MSPI: SCKM input
MSPI: SCKM output
I2C: SCL bi-direct
DSP0: GPIO0 input
DSP0: GPIO0 output
X
X
(1) (1)
input 5VT
output 4mA PP
input 5VT/output 4mA OD
input 5VT
output 4mA OD
(1) undefined
input
7 MSPI: MISOM input
MSPI: MISOM output
I2C: SDA bi-direct
DSP0: GPIO1 input
DSP0: GPIO1 output
X
0 or 1
X
X
X
X
input 5VT
output 4mA OD
input 5VT/output 4mA OD
input 5VT
output 4mA PP
8 MSPI: MOSIM input
MSPI: MOSIM output
DSP0: GPIO2 input
DSP0: GPIO2 output
X
X X X input 5VT
output 4mA OD
input 5VT
output 4mA OD
9 MSPI: SSM input
DSP0: GPIO3 input
DSP0: GPIO3 output
X
X
XX
input 5VT
input 5VT
output 4mA PP
10 DSPI: SCKD input
DSPI: SCKD output
DSP0: GPIO4 input
DSP0: GPIO4 output
X
X X X input 5VT
output 4mA PP
input 5VT
output 4mA PP
N° Name Type Description
PIN DESCRIPTION
(continued)
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA7500A

Mfr. #:
Buy TDA7500A
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
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